st,stm32g4-pll-clock

Description

STM32G4 main PLL.

It can take one of clk_hse or clk_hsi as input clock, with
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
  f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48MCLK (for USB, RNG)
  f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

The PLL output frequency must not exceed 170 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

div-m

int

 
Division factor for PLL input clock
Valid range: 1 - 16

This property is required.

mul-n

int

 
Main PLL multiplication factor for VCO
Valid range: 8 - 127

This property is required.

div-p

int

 
Main PLL division factor for ADC
Valid range: 2 - 31

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div-q

int

 
Division factor for PLLx_Q.

Legal values: 2, 4, 6, 8

div-r

int

 
Division factor for PLLx_R.

Legal values: 2, 4, 6, 8

post-div-r

int

 
Division factor after PLLSAI2_R for LTDC pixel clock. Only available
on PLLSAI2 of STM32L4+ series. If available, this property must be
provided when PLLSAI2_R is enabled (i.e., if `div-r` is provided).

Legal values: 2, 4, 8, 16