st,stm32h5-pll-clock

Overview

Name:

st,stm32h5-pll-clock

Vendor:

STMicroelectronics

Used in:

List of boards using this compatible

Description

STM32H5 PLL.

It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.

These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_Px) = f(VCOx clock) / PLLPx   -> pllx_p_ck ((pll1_p_ck : sys_ck))
  f(PLL_Qx) = f(VCOx clock) / PLLQx   -> pllx_q_ck
  f(PLL_Rx) = f(VCOx clock) / PLLRx   -> pllx_r_ck

    with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)

f(VCOx clock) depends on the PLL. VCO1 maximum frequency is 560 MHz while
VCO2 and VCO3 (if applicable) have a maximum frequency of 420 Mhz.

The PLL output frequency must not exceed 420 MHz.

PLL3 is not available on stm32h503.

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
div-p	int	PLL division factor for pllx_p_ck Note: For PLL1, P division factor must be even. Value range: 1 to 128
#clock-cells	int	Number of items to expect in a Clock specifier This property is required. Constant value: 0
div-m	int	Division factor for PLLx input clock This property is required. Value range: 1 to 63
mul-n	int	Main PLL multiplication factor for VCOx This property is required. Value range: 4 to 512
div-q	int	PLL division factor for pllx_q_ck Value range: 1 to 128
div-r	int	PLL division factor for pllx_r_ck Value range: 1 to 128
fracn	int	PLLx FRACN value Value range: 0 to 8191