st,stm32h7rs-pll-clock

Vendor: STMicroelectronics

Description

PLL node binding for STM32H7RS devices

It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.

These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

Each PLL can have up to 5 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_Px) = f(VCOx clock) / PLLPx   -> pllx_p_ck ((pll1_p_ck : sys_ck))
  f(PLL_Qx) = f(VCOx clock) / PLLQx   -> pllx_q_ck
  f(PLL_Rx) = f(VCOx clock) / PLLRx   -> pllx_r_ck
  f(PLL_Sx) = f(VCOx clock) / PLLSx   -> pllx_s_ck
  f(PLL_Tx) = f(VCOx clock) / PLLTx   -> pllx_t_ck (only for PLL2)

    with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)

Properties

Properties not inherited from the base binding file.

Name

Type

Details

div-s

int

 
PLL division factor for pllx_s_ck : valid for PLL1, 2, 3
Valid range: 1 - 8

div-t

int

 
PLL division factor for pllx_t_ck : valid for PLL2
Valid range: 1 - 8

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div-m

int

 
Division factor for PLLx
input clock
Valid range: 1 - 63

This property is required.

mul-n

int

 
Main PLL multiplication factor for VCOx
Valid range: 4 - 512

This property is required.

div-p

int

 
PLL division factor for pllx_p_ck
Valid range: 1 - 128

div-q

int

 
PLL division factor for pllx_q_ck
Valid range: 1 - 128

div-r

int

 
PLL division factor for pllx_r_ck
Valid range: 1 - 128

fracn

int

 
PLLx FRACN value
Valid range: 0 - 8191