st,stm32l4-pll-clock

Description

PLL node binding for STM32L4 and L5 devices

It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.

These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLLx_P) = f(VCO clock) / PLLxP
  f(PLLx_Q) = f(VCO clock) / PLLxQ
  f(PLLx_R) = f(VCO clock) / PLLxR

    with f(VCO clock) = f(PLL clock input) × (PLLxN / PLLxM)

The PLL output frequency must not exceed 80 MHz.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

div-m

int

 
Division factor for the PLL input clock.
On L4 series, the division factor M is shared between PLL, PLLSAI1
and PLLSAI2. For these series, valid range is 1 - 8.
On L4+ and L5 series, each PLL has an independent division factor M.
For these series, valid range is 1 - 16.

This property is required.

mul-n

int

 
Multiplication factor for VCO. Valid range is 8 - 127 for L4+
series and 8 - 86 for other series.

This property is required.

div-p

int

 
Division factor for PLLx_P. Valid values are 2 - 31 for all
series except L47x/48x for which valid values are 7 or 17.

div-q

int

 
Division factor for PLLx_Q.

Legal values: 2, 4, 6, 8

div-r

int

 
Division factor for PLLx_R.

Legal values: 2, 4, 6, 8

post-div-r

int

 
Division factor after PLLSAI2_R for LTDC pixel clock. Only available
on PLLSAI2 of STM32L4+ series. If available, this property must be
provided when PLLSAI2_R is enabled (i.e., if `div-r` is provided).

Legal values: 2, 4, 8, 16