st,stm32wb-pll-clock

Description

STM32WB and STM32WL PLL node.

It can be used to describe 2 different PLLs: PLL, PLLSAI1.
Only main PLL is supported for now.

These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

Each PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_P) = f(VCO clock) / PLLP  --> PLLPCLK
  f(PLL_Q) = f(VCO clock) / PLLQ  --> PLLQCLK
  f(PLL_R) = f(VCO clock) / PLLR  --> PLLRCLK (System Clock)

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

The PLL output frequency must not exceed:
        - 64 MHz on STM32WB
        - 62 MHz on STM32WL

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

Constant value: 0

div-m

int

 
Main PLL division factor for PLL input clock

This property is required.

Value range: 1 to 8

mul-n

int

 
Main PLL multiplication factor for VCO

This property is required.

Value range: 6 to 127

div-p

int

 
Main PLL division factor for PLLPCLK

Value range: 2 to 32

div-q

int

 
Main PLL division factor for PLLQCLK

Value range: 2 to 8

div-r

int

 
Main PLL division factor for PLLRCLK (system clock)

This property is required.

Value range: 2 to 8