st,stm32wba-rcc

Vendor: STMicroelectronics

Description

STM32WBA RCC (Reset and Clock controller).

This node is in charge of system clock ('SYSCLK') source selection and controlling
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.

Configuring STM32 Reset and Clock controller node:

System clock source should be selected amongst the clock nodes available in "clocks"
node (typically 'clk_hse, clk_hsi', 'pll').
Core clock frequency should also be defined, using "clock-frequency" property.
Note:
        Core clock frequency  = SYSCLK / AHB prescaler
Last, peripheral bus clocks (typically PCLK1, PCLK2, PCLK7) should be configured using
matching prescaler properties.
Here is an example of correctly configured rcc node:
&rcc {
         clocks = <&pll>;                   /* Select pll as SYSCLK source */
         ahb-prescaler = <2>;
         clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
         apb1-presacler = <1>;
         apb2-presacler = <1>;
         apb7-presacler = <7>;
}

Specifying a gated clock:

To specify a gated clock, a peripheral should define a "clocks" property such as:
... {
         ...
         clocks = <&rcc STM32_CLOCK(APB2, 5)>;
         ...
}

After the phandle referring to rcc node, use the STM32_CLOCK() macro which accepts
two parameters: the first specifies the bus on which the peripheral is attached, and
the second indicates the bit number controlling the peripheral clock gate in that
bus's control register in RCC. As an example, the snippet above indicates that the
peripheral gate is controlled by bit 5 in RCC_APB2ENR (USART6EN on STM32F401).
The gated clock is required when accessing to the peripheral controller is needed
(generally for configuring the device). If dual clock domain is not used, it is
also used for peripheral operation.

Note: in situations where more than one bit is required, use the explicit form:
... {
         ...
         clocks = <&rcc STM32_CLOCK_BUS_APB2 ((1 << 14) | (1 << 7))>;
         ...
}
where 14 and 7 are the bits that control the peripheral clock gate.
(You can have more than two bits, and they do not have to be contiguous).


Specifying an alternate clock source:

Specifying an alternate source clock could be done by adding a clock specifier to the
clock property:
... {
         ...
         clocks = <&rcc STM32_CLOCK(APB2, 5)>,
                      <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
         ...
}
In this example I2C1 device is assigned HSI as clock source.
It is device driver's responsibility to query and use clock source information in
accordance with clock_control API specifications.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.

Constant value: 2

clock-frequency

int

 
default frequency in Hz for clock output (HCLK1)

This property is required.

ahb-prescaler

int

 
Common AHB1, AHB2, AHB4 prescaler. Defines actual core clock frequency
(HCLK) based on system frequency input. AKA HPRE.
The HCLK clocks CPU, AHB1, AHB2, memories and DMA.

This property is required.

Legal values: 1, 2, 4, 8, 16

ahb5-prescaler

int

 
AHB5 prescaler. Defines actual core clock frequency (HCLK5) based on
system frequency input. It is used to limit HCLK5 below 32MHz.
Only required when SysClock source is PLL1.
AKA HPRE5.

Legal values: 1, 2, 3, 4, 6

apb1-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

apb2-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

apb7-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

ahb5-div

boolean

 
AHB5 divider. Applies only when SysClock source is HSI16 or HSE32.
When enabled, AHB5 clock is SysClock / 2.
When disabled, SysClock is not divided.

Specifier cell names

  • clock cells: bus, bits