ti,cdce937 (on i2c bus)

Description

TI CDCE937 clock generator driver.

Properties

Top level properties

These property descriptions apply to “ti,cdce937” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

Name

Type

Details

input-clock-type

string

This property is required.

Legal values: crystal, vcxo, lvcmos

input-frequency

int

Input frequency in Hz to the CDCE9xx (8000000 Hz - 32000000 Hz for the crystal,
up to 160000000 Hz for a lvcmos clock).

This property is required.

Value range: 8000000 to 160000000

xtal-load-pf

int

Crystal load-capacitor value to fine-tune performance on a board, or to compensate
for external influences.

Default value: 10

Value range: 0 to 20

keep-y1-enabled

boolean

Ensure that output Y1 is never disabled. Important if the MCU is clocked by this output.

pdiv1

int

Divider for output Y1 (input is always input clock)

Value range: 1 to 1023

supply-gpios

phandle-array

GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

Child node properties

Name

Type

Details

clock-mult

int

N multiplier for this PLL.

This property is required.

Value range: 1 to 4095

clock-div

int

M divider (pre-divider) for this PLL.

This property is required.

Value range: 1 to 511

ssc

string

Spread spectrum clocking configuration for this PLL.

Default value: off

Legal values: off, down-0.25, down-0.5, down-0.75, down-1, down-1.25, down-1.5, down-2, center-0.25, center-0.5, center-0.75, center-1, center-1.25, center-1.5, center-2

first-divider

int

Output divider for the first output (Pdiv2, Pdiv4,...).

Value range: 1 to 127

second-divider

int

Output divider for the second output (Pdiv3, Pdiv5,...).

Value range: 1 to 127