espressif,riscv

Description

Espressif RISC-V CPU

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-source

int

 
Defines the CPU clock source, each corresponding to different frequencies:
- 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
- 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
320 MHz or 480 MHz.
- 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with
frequency of 17.5 MHz.

This property is required.

Legal values: 0, 1, 2

xtal-freq

int

 
Value of the external XTAL connected to ESP32. This is typically 40 MHz.

This property is required.

Legal values: 26000000, 32000000, 40000000

mmu-type

string

 
Memory Management Unit (MMU)

Legal values: riscv,sv32, riscv,sv39, riscv,sv48, riscv,none

riscv,isa-base

string

 
The base ISA implemented by the hart.

This property is required.

Legal values: rv32i, rv32e, rv64i, rv128i

riscv,isa-extensions

string-array

 
Extensions supported by the hart. Take a look at
https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
and https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
for a list of possible extensions. Not all options listed there are
necessarily supported by Zephyr.

This property is required.

clock-frequency

int

 
Clock frequency in Hz

cpu-power-states

phandles

 
List of power management states supported by this cpu

i-cache-line-size

int

 
i-cache line size

d-cache-line-size

int

 
d-cache line size

enable-method

string

 
Enable method for cpu, either it is "psci" or "spin-table"