openisa,zero-ri5cy

Description

OpenISA Zero-RI5CY core

Properties

Properties not inherited from the base binding file.

Name

Type

Details

mmu-type

string

Memory Management Unit (MMU)

Legal values: 'riscv,sv32', 'riscv,sv39', 'riscv,sv48', 'riscv,none'

riscv,isa-base

string

The base ISA implemented by the hart.

This property is required.

Legal values: 'rv32i', 'rv32e', 'rv64i', 'rv128i'

riscv,isa-extensions

string-array

Extensions supported by the hart. Take a look at
https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
and https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
for a list of possible extensions. Not all options listed there are
necessarily supported by Zephyr.

This property is required.

clock-frequency

int

Clock frequency in Hz

cpu-power-states

phandles

List of power management states supported by this cpu

i-cache-line-size

int

i-cache line size

d-cache-line-size

int

d-cache line size

enable-method

string

Enable method for cpu, either it is "psci" or "spin-table"