infineon,autanalog-ctdac

Description

PSOC Edge AutAnalog CT DAC

Infineon PSOC Edge AutAnalog CT DAC (Continuous Time Digital-to-Analog Converter)

The CT DAC is a 12-bit continuous-time segmented DAC within the AutAnalog subsystem.
It supports multiple output topologies (direct, buffered internal, buffered external),
configurable voltage reference sources, and optional sample-and-hold operation.

The driver exposes:
  - FW channel (#15): Direct value writes via the standard Zephyr DAC API.
    This is the default channel for simple DAC output (channel 15).
  - Waveform channels (#0-#14): Autonomous waveform output via the AC state
    machine. Channel IDs 0-14 map directly to DAC hardware channels 0-14.
    These use look-up table (LUT) ranges configured via child nodes and
    waveform data loaded at runtime.

The AutAnalog CT DAC is part of the AutAnalog subsystem, which must be set up
before initializing the CTDAC.

Properties

Top level properties

These property descriptions apply to “infineon,autanalog-ctdac” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

Name	Type	Details
`#io-channel-cells`	`int`	Number of cells in an io-channel specifier. This property is required. Constant value: `1`
`clk-dst`	`int`	Peripheral clock destination ID for this CTDAC instance. This property is required.
`vref-source`	`int`	Selects the reference voltage source for the DAC. Use IFX_AUTANALOG_CTDAC_VREF_* constants from <dt-bindings/dac/infineon-autanalog-ctdac.h>. IFX_AUTANALOG_CTDAC_VREF_VDDA (0x100) - Vdda supply (1.8V typical) IFX_AUTANALOG_CTDAC_VREF_VBGR (0) - Band-gap reference (0.9V typical) IFX_AUTANALOG_CTDAC_VREF_CTB0_OA0 (1) - CTB0 opamp 0 output IFX_AUTANALOG_CTDAC_VREF_CTB0_OA1 (2) - CTB0 opamp 1 output IFX_AUTANALOG_CTDAC_VREF_CTB1_OA0 (3) - CTB1 opamp 0 output IFX_AUTANALOG_CTDAC_VREF_CTB1_OA1 (4) - CTB1 opamp 1 output IFX_AUTANALOG_CTDAC_VREF_PRB_OUT0 (6) - PRB Vref0 IFX_AUTANALOG_CTDAC_VREF_PRB_OUT1 (7) - PRB Vref1 Default value: `0x100` Legal values: `0x100`, `0`, `1`, `2`, `3`, `4`, `6`, `7`
`topology`	`int`	Selects the DAC output topology. Use IFX_AUTANALOG_CTDAC_TOPO_* constants from <dt-bindings/dac/infineon-autanalog-ctdac.h>. IFX_AUTANALOG_CTDAC_TOPO_DIRECT (0) - Direct output IFX_AUTANALOG_CTDAC_TOPO_DIRECT_TRACK_CAP (1) - Direct with track capacitor IFX_AUTANALOG_CTDAC_TOPO_DIRECT_TRACK_HOLD (2) - Direct with track and hold capacitors IFX_AUTANALOG_CTDAC_TOPO_BUFFERED_INTERNAL (3) - Buffered, internal connections only IFX_AUTANALOG_CTDAC_TOPO_BUFFERED_EXTERNAL (4) - Buffered, internal and external Default value: `4` Legal values: `0`, `1`, `2`, `3`, `4`
`ref-buf-pwr`	`int`	Power mode for the reference voltage buffer. Use IFX_AUTANALOG_CTDAC_REF_BUF_PWR_* constants from <dt-bindings/dac/infineon-autanalog-ctdac.h>. IFX_AUTANALOG_CTDAC_REF_BUF_PWR_OFF (0) - Buffer OFF IFX_AUTANALOG_CTDAC_REF_BUF_PWR_ULTRA_LOW (1) - 15uA, 30kHz GBW IFX_AUTANALOG_CTDAC_REF_BUF_PWR_ULTRA_LOW_RAIL (2) - Charge pump ON, 35uA, 30kHz GBW IFX_AUTANALOG_CTDAC_REF_BUF_PWR_LOW_RAIL (4) - Charge pump ON, 150uA, 350kHz GBW IFX_AUTANALOG_CTDAC_REF_BUF_PWR_MEDIUM_RAIL (6) - Charge pump ON, 200uA, 700kHz GBW IFX_AUTANALOG_CTDAC_REF_BUF_PWR_HIGH (7) - 400uA, 1.75MHz GBW (Vref <= 0.9V) IFX_AUTANALOG_CTDAC_REF_BUF_PWR_HIGH_RAIL (8) - Charge pump ON, 600uA, 1.75MHz GBW IFX_AUTANALOG_CTDAC_REF_BUF_PWR_ULTRA_HIGH_RAIL (10) - Charge pump ON, 800uA, 2.8MHz GBW Set to OFF (0) when vref-source is "vdda", since the Vdda path does not use the reference buffer. Default value: `0` Legal values: `0`, `1`, `2`, `4`, `6`, `7`, `8`, `10`
`out-buf-pwr`	`int`	Power mode for the output voltage buffer. Use IFX_AUTANALOG_CTDAC_OUT_BUF_PWR_* constants from <dt-bindings/dac/infineon-autanalog-ctdac.h>. IFX_AUTANALOG_CTDAC_OUT_BUF_PWR_OFF (0) - Buffer OFF IFX_AUTANALOG_CTDAC_OUT_BUF_PWR_ULTRA_LOW (1) - 15uA, drive 10uA IFX_AUTANALOG_CTDAC_OUT_BUF_PWR_ULTRA_LOW_RAIL (2) - Charge pump ON, 35uA, drive 10uA IFX_AUTANALOG_CTDAC_OUT_BUF_PWR_LOW_RAIL (4) - Charge pump ON, 150uA, drive 100uA IFX_AUTANALOG_CTDAC_OUT_BUF_PWR_MEDIUM_RAIL (6) - Charge pump ON, 200uA, drive 1mA IFX_AUTANALOG_CTDAC_OUT_BUF_PWR_HIGH_RAIL (8) - Charge pump ON, 600uA, drive 1mA IFX_AUTANALOG_CTDAC_OUT_BUF_PWR_ULTRA_HIGH_RAIL (10) - Charge pump ON, 800uA, drive 10mA Must be non-OFF when topology is "buffered-internal" or "buffered-external". Default value: `0` Legal values: `0`, `1`, `2`, `4`, `6`, `8`, `10`
`lp-mode`	`boolean`	Request Low Power (LP) operation for the AutAnalog subsystem. When set, the parent AutAnalog MFD basic-mode STT enters LP operation for the AC states. LP mode is also activated if any other AutAnalog child peripheral (SAR ADC, CTB, PTCOMP, PRB) sets lp-mode. In advanced mode (ac-states), use the per-state ac-lp-mode property instead.
`lp-div-dac`	`int`	Low-power clock divider for the DAC. The actual divisor applied by the hardware is (lp-div-dac + 1). Valid range: 0..1023. Default value: `0`
`bottom-sel`	`boolean`	R-2R ladder bottom connection selector. When set, the bottom end of the R-2R resistor ladder is connected to Vref instead of Vssa.
`disabled-mode`	`boolean`	DAC output behavior when disabled. When set, the output drives Vssa or Vref (depending on bottom-sel) when the output is disabled. Otherwise the output is tri-stated.
`deglitch`	`boolean`	Enable the de-glitch functionality. When enabled, a switch on the output path blanks glitches during code transitions.
`deglitch-time`	`int`	De-glitch time in DAC clock cycles (actual value = deglitch-time + 1). Only used when deglitch is enabled. Range 0..255. Default value: `0`
`sign`	`boolean`	When set, the DAC input data is interpreted as a signed 12-bit value (two's complement). Otherwise unsigned.
`sample-time`	`int`	Sample time in DAC clock cycles. Range 0..255. The actual sample time used by the hardware is (sample-time + 1). Default value: `0`
`step-val`	`array`	Step values for waveform address increment. Array of exactly 3 values (step-val[0], step-val[1], step-val[2]). Each waveform channel selects one via its step-sel property. Default value: `[0, 0, 0]`
`limit-cfg-0`	`array`	Range detection configuration for limit slot 0. Three-cell array: <condition low-threshold high-threshold>. Use IFX_AUTANALOG_CTDAC_LIMIT_* constants from <dt-bindings/dac/infineon-autanalog-ctdac.h> for the condition: IFX_AUTANALOG_CTDAC_LIMIT_BELOW (0) - Value < low IFX_AUTANALOG_CTDAC_LIMIT_INSIDE (1) - low <= Value < high IFX_AUTANALOG_CTDAC_LIMIT_ABOVE (2) - Value > high IFX_AUTANALOG_CTDAC_LIMIT_OUTSIDE (3) - Value < low OR Value >= high Waveform channels reference this slot via stat-sel = <1>.
`limit-cfg-1`	`array`	Range detection configuration for limit slot 1. Same format as limit-cfg-0. Referenced via stat-sel = <2>.
`limit-cfg-2`	`array`	Range detection configuration for limit slot 2. Same format as limit-cfg-0. Referenced via stat-sel = <3>.

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “infineon,autanalog-ctdac” compatible.

Name	Type	Details
`reg`	`array`	Base address offset of the CTDAC within the AutAnalog subsystem. This property is required. See Important properties for more information.
`clocks`	`phandle-array`	Phandle to the peripheral clock divider node (infineon,peri-div) that provides the CTDAC peripheral clock. The divider is in PERI0 group 2 (CLK_HF9). Each CTDAC instance needs its own divider channel: DAC0 -> PCLK_PASS_CLOCK_DAC0 (peri0, group 2, index 0) DAC1 -> PCLK_PASS_CLOCK_DAC1 (peri0, group 2, index 1) This property is required.
`status`	`string`	Indicates the operational status of the hardware or other resource that the node represents. In particular: - "okay" means the resource is operational and, for example, can be used by device drivers - "disabled" means the resource is not operational and the system should treat it as if it is not present For details, see "2.3.4 status" in Devicetree Specification v0.4. Legal values: `okay`, `disabled`, `reserved`, `fail`, `fail-sss` See Important properties for more information.
`compatible`	`string-array`	This property is a list of strings that essentially define what type of hardware or other resource this devicetree node represents. Each device driver checks for specific compatible property values to find the devicetree nodes that represent resources that the driver should manage. The recommended format is "vendor,device", The "vendor" part is an abbreviated name of the vendor. The "device" is usually from the datasheet. The compatible property can have multiple values, ordered from most- to least-specific. Having additional values is useful when the device is a specific instance of a more general family, to allow the system to match the most specific driver available. For details, see "2.3.1 compatible" in Devicetree Specification v0.4. This property is required. See Important properties for more information.
`reg-names`	`string-array`	Optional names given to each register block in the "reg" property. For example: / { soc { #address-cells = <1>; #size-cells = <1>; uart@1000 { reg = <0x1000 0x2000>, <0x3000 0x4000>; reg-names = "foo", "bar"; }; }; }; The uart@1000 node has two register blocks: - one with base address 0x1000, size 0x2000, and name "foo" - another with base address 0x3000, size 0x4000, and name "bar"
`interrupts`	`array`	Information about interrupts generated by the device, encoded as an array of one or more interrupt specifiers. The format of the data in this property varies by where the device appears in the interrupt tree. Devices with the same "interrupt-parent" will use the same format in their interrupts properties. For details, see "2.4 Interrupts and Interrupt Mapping" in Devicetree Specification v0.4. See Important properties for more information.
`interrupts-extended`	`compound`	Extended interrupt specifier for device, used as an alternative to the "interrupts" property. For details, see "2.4 Interrupts and Interrupt Mapping" in Devicetree Specification v0.4.
`interrupt-names`	`string-array`	Optional names given to each interrupt generated by a device. The interrupts themselves are defined in either "interrupts" or "interrupts-extended" properties. For details, see "2.4 Interrupts and Interrupt Mapping" in Devicetree Specification v0.4.
`interrupt-parent`	`phandle`	If present, this refers to the node which handles interrupts generated by this device. For details, see "2.4 Interrupts and Interrupt Mapping" in Devicetree Specification v0.4.
`label`	`string`	Human readable string describing the device. Use of this property is deprecated except as needed on a case-by-case basis. For details, see "4.1.2 Miscellaneous Properties" in Devicetree Specification v0.4. See Important properties for more information.
`clock-names`	`string-array`	Optional names given to each clock provider in the "clocks" property.
`#address-cells`	`int`	This property encodes the number of <u32> cells used by address fields in "reg" properties in this node's children. For details, see "2.3.5 #address-cells and #size-cells" in Devicetree Specification v0.4.
`#size-cells`	`int`	This property encodes the number of <u32> cells used by size fields in "reg" properties in this node's children. For details, see "2.3.5 #address-cells and #size-cells" in Devicetree Specification v0.4.
`dma-coherent`	`boolean`	Indicates that the device is capable of coherent DMA operations. For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
`dmas`	`phandle-array`	DMA channel specifiers relevant to the device.
`dma-names`	`string-array`	Optional names given to the DMA channel specifiers in the "dmas" property.
`io-channels`	`phandle-array`	IO channel specifiers relevant to the device.
`io-channel-names`	`string-array`	Optional names given to the IO channel specifiers in the "io-channels" property.
`mboxes`	`phandle-array`	Mailbox / IPM channel specifiers relevant to the device.
`mbox-names`	`string-array`	Optional names given to the mbox specifiers in the "mboxes" property.
`power-domains`	`phandle-array`	Power domain specifiers relevant to the device.
`power-domain-names`	`string-array`	Optional names given to the power domain specifiers in the "power-domains" property.
`#power-domain-cells`	`int`	Number of cells in power-domains property
`hwlocks`	`phandle-array`	HW spinlock id relevant to the device.
`hwlock-names`	`string-array`	Optional names given to the hwlock specifiers in the "hwlocks" property.
`zephyr,deferred-init`	`boolean`	Do not initialize device automatically on boot. Device should be manually initialized using device_init().
`wakeup-source`	`boolean`	Property to identify that a device can be used as wake up source. When this property is provided a specific flag is set into the device that tells the system that the device is capable of wake up the system. Wake up capable devices are disabled (interruptions will not wake up the system) by default but they can be enabled at runtime if necessary.
`zephyr,pm-device-runtime-auto`	`boolean`	Automatically configure the device for runtime power management after the init function runs.
`zephyr,disabling-power-states`	`phandles`	List of power states that will disable this device power.

Child node properties

Name	Type	Details
`start-addr`	`int`	Start address in the DAC look-up table (0..511). Required for waveform channels (reg 0-14).
`end-addr`	`int`	End address in the DAC look-up table (0..511). Must be >= start-addr. Required for waveform channels (reg 0-14).
`op-mode`	`int`	Waveform operating mode for this channel. Use IFX_AUTANALOG_CTDAC_OP_* constants from <dt-bindings/dac/infineon-autanalog-ctdac.h>. IFX_AUTANALOG_CTDAC_OP_OS_ONE_QUAD (0) - One-shot, one quadrant IFX_AUTANALOG_CTDAC_OP_OS_TWO_QUAD (1) - One-shot, two quadrant IFX_AUTANALOG_CTDAC_OP_OS_FOUR_QUAD (2) - One-shot, four quadrant IFX_AUTANALOG_CTDAC_OP_CONT_ONE_QUAD (3) - Continuous, one quadrant IFX_AUTANALOG_CTDAC_OP_CONT_TWO_QUAD (4) - Continuous, two quadrant IFX_AUTANALOG_CTDAC_OP_CONT_FOUR_QUAD (5) - Continuous, four quadrant IFX_AUTANALOG_CTDAC_OP_ADDR (6) - External address mode IFX_AUTANALOG_CTDAC_OP_DATA (7) - External data mode Default value: `3` Legal values: `0`, `1`, `2`, `3`, `4`, `5`, `6`, `7`
`sample-and-hold`	`boolean`	Enable sample-and-hold for this channel.
`step-sel`	`int`	Step value selector for address increment. Use IFX_AUTANALOG_CTDAC_STEP_SEL_* constants from <dt-bindings/dac/infineon-autanalog-ctdac.h>. IFX_AUTANALOG_CTDAC_STEP_SEL_DISABLED (0) - Step value is 1 (default) IFX_AUTANALOG_CTDAC_STEP_SEL_0 (1) - Use stepVal[0] IFX_AUTANALOG_CTDAC_STEP_SEL_1 (2) - Use stepVal[1] IFX_AUTANALOG_CTDAC_STEP_SEL_2 (3) - Use stepVal[2] Default value: `0` Legal values: `0`, `1`, `2`, `3`
`stat-sel`	`int`	Range detection / status selector. Use IFX_AUTANALOG_CTDAC_STAT_SEL_* constants from <dt-bindings/dac/infineon-autanalog-ctdac.h>. IFX_AUTANALOG_CTDAC_STAT_SEL_DISABLED (0) - No range validation IFX_AUTANALOG_CTDAC_STAT_SEL_0 (1) - Use chLimitCfg[0] IFX_AUTANALOG_CTDAC_STAT_SEL_1 (2) - Use chLimitCfg[1] IFX_AUTANALOG_CTDAC_STAT_SEL_2 (3) - Use chLimitCfg[2] Default value: `0` Legal values: `0`, `1`, `2`, `3`
`reg`	`array`	Channel identifier. This property is required. See Important properties for more information.
`zephyr,resolution`	`int`	DAC resolution to be used for the channel.
`zephyr,buffered`	`boolean`	Enable output buffer for the channel.
`zephyr,internal`	`boolean`	Enable internal output path for the channel.
`zephyr,vref-mv`	`int`	This property can be used to specify the voltage (in millivolts) of the reference selected for this channel, so that applications can get that value if needed for some calculations.

Specifier cell names

io-channel cells: output