ilitek,ili9341 (on mipi-dbi bus)

Vendor: ILI Technology Corporation (ILITEK)

Description

ILI9341 320x240 display controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

ifmode

uint8-array

 
RGB interface signal control (IFMOD) register value.

Default value: [64]

ifctl

uint8-array

 
Interface control (IFCTL) register value.

Default value: [1, 0, 0]

pwctrla

uint8-array

 
Power control A (PWCTRLA) register value.

Default value: [57, 44, 0, 52, 2]

pwctrlb

uint8-array

 
Power control B (PWCTRLB) register value.

Default value: [0, 139, 48]

pwseqctrl

uint8-array

 
Power on sequence control (PWSEQCTRL) register value.

Default value: [85, 1, 35, 1]

timctrla

uint8-array

 
Driver timing control A (TIMCTRLA) register value.

Default value: [132, 17, 122]

timctrlb

uint8-array

 
Driver timing control B (TIMCTRLB) register value.

Default value: [0, 0]

pumpratioctrl

uint8-array

 
Pump ratio control (PUMPRATIOCTRL) register value.

Default value: [16]

enable3g

uint8-array

 
Enable 3G (ENABLE3G) register value.

Default value: [2]

etmod

uint8-array

 
Entry Mode Set (ETMOD) register value.

Default value: [6]

gamset

uint8-array

 
Gamma set (GAMSET) register value.

Default value: [1]

frmctr1

uint8-array

 
Frame rate control (in normal mode / full colors) (FRMCTR1) register value.

Default value: [0, 27]

disctrl

uint8-array

 
Display function control (DISCTRL) register value. Note that changing default SS bit value (0) may interfere with display rotation.

Default value: [10, 130, 39, 4]

pwctrl1

uint8-array

 
Power control 1 (PWCTRL1) register values.

Default value: [33]

pwctrl2

uint8-array

 
Power control 2 (PWCTRL2) register values.

Default value: [16]

vmctrl1

uint8-array

 
VCOM control 1 (VMCTRL1) register values.

Default value: [49, 60]

vmctrl2

uint8-array

 
VCOM control 2 (VMCTRL2) register values.

Default value: [192]

pgamctrl

uint8-array

 
Positive gamma correction (PGAMCTRL) register values.

Default value: [15, 34, 31, 10, 14, 6, 77, 118, 59, 3, 14, 4, 19, 14, 12]

ngamctrl

uint8-array

 
Negative gamma correction (NGAMCTRL) register values.

Default value: [12, 35, 38, 4, 16, 4, 57, 36, 75, 3, 11, 11, 51, 55, 15]

pixel-format

int

 
Display pixel format. Note that when RGB888 pixel format is selected only 6 color bits are actually used being in practice equivalent to RGB666.

Legal values: 0, 1

rotation

int

 
Display rotation (CW) in degrees. If not defined, rotation is off by default.

Legal values: 0, 90, 180, 270

display-inversion

boolean

 
Display inversion mode. Every bit is inverted from the frame memory to the display.

duplex

int

 
SPI Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Selecting half duplex allows to use SPI MOSI as a bidirectional line,
typically used when only one data line is connected.
Use the macros, not the actual enum value. Here is the concordance
list (see dt-bindings/spi/spi.h)
  0    SPI_FULL_DUPLEX
  2048 SPI_HALF_DUPLEX

mipi-cpol

boolean

 
SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.

mipi-cpha

boolean

 
SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.

mipi-hold-cs

boolean

 
In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.

mipi-max-frequency

int

 
Maximum clock frequency of device's MIPI interface in Hz

mipi-mode

string

 
MIPI DBI mode in use. These definitions should match those in
dt-bindings/mipi_dbi/mipi_dbi.h

Legal values: 'MIPI_DBI_MODE_SPI_3WIRE', 'MIPI_DBI_MODE_SPI_4WIRE', 'MIPI_DBI_MODE_6800_BUS_16_BIT', 'MIPI_DBI_MODE_6800_BUS_9_BIT', 'MIPI_DBI_MODE_6800_BUS_8_BIT', 'MIPI_DBI_MODE_8080_BUS_16_BIT', 'MIPI_DBI_MODE_8080_BUS_9_BIT', 'MIPI_DBI_MODE_8080_BUS_8_BIT'

te-mode

string

 
MIPI DBI tearing enable signal mode. Defaults to disabled.

Default value: MIPI_DBI_TE_NO_EDGE

Legal values: 'MIPI_DBI_TE_NO_EDGE', 'MIPI_DBI_TE_RISING_EDGE', 'MIPI_DBI_TE_FALLING_EDGE'

te-delay

int

 
Delay in microseconds to wait before transmitting display data after a
tearing enable synchronization signal is seen. Defaults to 0 since most
controllers will not need a delay.

supply-gpios

phandle-array

 
GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

 
Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

height

int

 
Height of the panel driven by the controller, with the units in pixels.

This property is required.

width

int

 
Width of the panel driven by the controller, with the units in pixels.

This property is required.