This is the documentation for the latest (main) development branch of Zephyr. If you are looking for the documentation of previous releases, use the drop-down menu on the left and select the desired version.

sitronix,st7735r (on mipi-dbi bus)

Vendor: Sitronix Technology Corporation

Description

ST7735R/ST7735S 160x128 (max) display controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

supply-gpios

phandle-array

GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

mipi-max-frequency

int

Maximum clock frequency of device's MIPI interface in Hz

mipi-mode

int

MIPI DBI mode in use. Use the macros, not the actual enum value. Here is
the concordance list (see dt-bindings/mipi_dbi/mipi_dbi.h)
  1     MIPI_DBI_MODE_SPI_3WIRE
  2     MIPI_DBI_MODE_SPI_4WIRE

Legal values: 1, 2

duplex

int

SPI Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Selecting half duplex allows to use SPI MOSI as a bidirectional line,
typically used when only one data line is connected.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0    SPI_FULL_DUPLEX
  2048 SPI_HALF_DUPLEX

mipi-cpol

boolean

SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.

mipi-cpha

boolean

SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.

mipi-hold-cs

boolean

In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.

height

int

Height of the panel driven by the controller, with the units in pixels.

This property is required.

width

int

Width of the panel driven by the controller, with the units in pixels.

This property is required.

x-offset

int

The column offset in pixels of the LCD to the controller memory

This property is required.

y-offset

int

The row offset in pixels of the LCD to the controller memory

This property is required.

madctl

int

Memory Data Access Control

colmod

int

Interface Pixel Format

Default value: 6

pwctr1

uint8-array

Power Control 1 Parameter

Default value: [180, 20, 4]

pwctr2

uint8-array

Power Control 2 Parameter

Default value: [192]

pwctr3

uint8-array

Power Control 3 Parameter

Default value: [10, 0]

pwctr4

uint8-array

Power Control 4 Parameter

Default value: [138, 38]

pwctr5

uint8-array

Power Control 5 Parameter

Default value: [138, 238]

gamctrp1

uint8-array

Positive Voltage Gamma Control Parameter

This property is required.

gamctrn1

uint8-array

Negative Voltage Gamma Control Parameter

This property is required.

frmctr1

uint8-array

Frame rate control (normal mode / full colors)

Default value: [5, 58, 58]

frmctr2

uint8-array

Frame rate control (idle mode / 8 colors)

Default value: [5, 58, 58]

frmctr3

uint8-array

Frame rate control (partial mode / full colors)

Default value: [5, 58, 58, 5, 58, 58]

caset

uint8-array

Column Address Set

Default value: [0, 0, 0, 127]

raset

uint8-array

Row Address Set

Default value: [0, 0, 0, 159]

vmctr1

int

VCOM Control 1

Default value: 10

invctr

int

Display Inversion Control
Set dot inversion or line inversion for each normal/idle/partial mode.

Default value: 7

inversion-on

boolean

Enable Display Inversion
Make a drawing with the inverted color of the frame memory.

rgb-is-inverted

boolean

Inverting color format order (RGB->BGR or BGR->RGB)
In the case of enabling this option, API reports pixel-format in capabilities
as the inverted value of the RGB pixel-format specified in MADCTL.
This option is convenient for supporting displays with bugs
where the actual color is different from the pixel format of MADCTL.