wch,wch-dma

Vendor: WinChipHead

Note

An implementation of a driver matching this compatible is available in drivers/dma/dma_wch.c.

Description

These nodes are “dma” bus nodes.

WCH DMA controller

The WCH DMA controller is a general-purpose direct memory access controller
featuring between 7 and 11 independent channels.
Every channel is capable of memory-to-memory, memory-to-peripheral, and
peripheral-to-memory access.

Mapping of peripheral requests to DMA channels is limited and SoC specific.
Commonly, each peripheral request maps to just a single DMA channel.
The controller supports 8, 16, and 32 bit width memory access.

It is present on WCH CH32V and CH32X series SoCs.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

#dma-cells

int

Number of items to expect in a DMA specifier

This property is required.

Constant value: 1

dma-channel-mask

int

Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.

dma-channels

int

Number of DMA channels supported by the controller

dma-requests

int

Number of DMA request signals supported by the controller.

dma-buf-addr-alignment

int

Memory address alignment requirement for DMA buffers used by the controller.

dma-buf-size-alignment

int

Memory size alignment requirement for DMA buffers used by the controller.

dma-copy-alignment

int

Minimal chunk of data possible to be copied by the controller.

Specifier cell names

  • dma cells: channel