nxp,espi
Description
These nodes are “espi” bus nodes.
NXP MCX A series eSPI target controller.
The peripheral has up to 5 configurable I/O ports.
Each port is described by a child node whose reg property gives
the hardware port index (0-4).
Properties
Top level properties
These property descriptions apply to “nxp,espi” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
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Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.
This property is required. |
|
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Names for the provided states. The number of names needs to match the
number of states.
This property is required. |
|
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SRAM base address used by the eSPI hardware for mailbox and
OOB DMA buffers. Must be naturally aligned and accessible
by the eSPI bus-master engine.
This property is required. |
|
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Upper 16-bit base address for ports that select BASE0
addressing via the PnADDR register. Combined with the
port's io-addr to form the full host-side address.
Default value: |
|
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Upper 16-bit base address for ports that select BASE1
addressing via the PnADDR register. Combined with the
port's io-addr to form the full host-side address.
Default value: |
|
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Maximum OOB channel payload size in bytes advertised to the host
through the ESPICAP.OOBMX capability field. This is a capability
ceiling: the host can only negotiate a value less than or equal to
this. The default matches the hardware/HAL reset capability.
Default value: Legal values: |
|
|
Maximum flash channel payload size in bytes advertised to the host
through the ESPICAP.FLASHMX capability field. This is a capability
ceiling: the host can only negotiate a value less than or equal to
this. The default matches the hardware/HAL reset capability.
Default value: Legal values: |
|
|
Maximum peripheral channel payload size in bytes advertised to the host
through the ESPICAP.MEMMX capability field. This is a capability
ceiling: the host can only negotiate a value less than or equal to
this. The default matches the hardware/HAL reset capability.
Default value: Legal values: |
|
|
Maximum target read request size in bytes advertised to the host
through the ESPICAP.TRGT_REQ_SIZE_SUPP capability field. This is a
capability ceiling: the host can only negotiate a value less than or
equal to this. The default matches the hardware/HAL reset capability.
Default value: Legal values: |
|
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Target-Attached-Flash minimum erase sector size in kilobytes advertised
to the host through the ESPICAP.SAFERA capability field. The default
matches the hardware/HAL reset capability.
Default value: Legal values: |
|
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Pin configuration/s for the second state. See pinctrl-0.
|
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Pin configuration/s for the third state. See pinctrl-0.
|
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Pin configuration/s for the fourth state. See pinctrl-0.
|
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Pin configuration/s for the fifth state. See pinctrl-0.
|
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,espi” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
This property is required. |
|
|
Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
|
|
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
|
|
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Information used to define a mapping (or translation) between the address
space of a bus (the "child address space") and the address space of the
bus node's parent (the "parent address space").
The "ranges" property is typically empty, or a sequence of triplets
(child bus address, parent bus address, length).
If the "ranges" property is empty, it specifies that the parent and child
address spaces are identical and no address translation is required.
If the "ranges" property is not present in a bus node, it is assumed that
no mapping exists between children of the node and the parent address space.
For details, see "2.3.8 ranges" in Devicetree Specification v0.4.
|
|
|
Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
|
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Optional names given to each clock provider in the "clocks" property.
|
|
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
|
|
|
This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
|
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Indicates that the device is capable of coherent DMA operations.
For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
|
|
|
DMA channel specifiers relevant to the device.
|
|
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Optional names given to the DMA channel specifiers in the "dmas" property.
|
|
|
The dma-ranges provides a means of defining a mapping or translation between the
physical address space of the bus and the physical address space of the parent of the bus.
For details, see "2.3.9 dma-ranges" in Devicetree Specification v0.4.
|
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IO channel specifiers relevant to the device.
|
|
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Optional names given to the IO channel specifiers in the "io-channels" property.
|
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Mailbox / IPM channel specifiers relevant to the device.
|
|
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Optional names given to the mbox specifiers in the "mboxes" property.
|
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Power domain specifiers relevant to the device.
|
|
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Optional names given to the power domain specifiers in the "power-domains" property.
|
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Number of cells in power-domains property
|
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HW spinlock id relevant to the device.
|
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Optional names given to the hwlock specifiers in the "hwlocks" property.
|
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
|
|
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
|
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Automatically configure the device for runtime power management after the
init function runs.
|
|
|
List of power states that will disable this device power.
|
Child node properties
Name |
Type |
Details |
|---|---|---|
|
|
Hardware port index. The driver maps each child node to the hardware
port at that index in declaration order, so child nodes must cover
every index from 0 up to the highest used port without gaps.
Use port-type = <0x0> as a placeholder for any index in that range
that requires no active function.
This property is required. See Important properties for more information. |
|
|
Port function type. The hardware port slot number equals the position
of this child node in the sorted child list, so all indices from 0 to
the highest active port must be present.
0x0 = Unconfigured
0x1 = ACPI Endpoint
0x2 = ACPI Index-Data
0x4 = Bus Master Memory
0x5 = Bus Master Flash
0x8 = Mailbox Shared
0x9 = Mailbox Single
0xA = Mailbox Split
0xB = Mailbox OOB Split
0xC = Mailbox OEM
This property is required. Legal values: |
|
|
Host-side I/O address offset for this port.
Default value: |
|
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Byte offset from ram-base-addr for this port's DMA buffer.
Default value: |
|
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RAM buffer size in bytes for this port's DMA buffer.
Default value: Legal values: |
|
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Index register offset for ACPI Index-Data ports.
Default value: |