microchip,vsc8541 (on mdio bus)

Description

Single Port Gigabit Ethernet Copper PHY with GMII/RGMII/MII/RMII Interfaces

Properties

Properties not inherited from the base binding file.

Name

Type

Details

reset-gpios

phandle-array

GPIO connected to MAC PHY reset signal pin. Reset is active low.

microchip,interface-type

string

Which type of phy connection the phy is set up for

This property is required.

Legal values: mii, rmii, gmii, rgmii

microchip,rgmii-rx-clk-delay

int

Used to configure the RX clock delay for RGMII interface. The value can be
0 to 7. Refer to the datasheet for more details on the delay settings.

Default value: 5

microchip,rgmii-tx-clk-delay

int

Used to configure the TX clock delay for RGMII interface. The value can be
0 to 7. Refer to the datasheet for more details on the delay settings.

Default value: 5

default-speeds

string-array

The selected speeds are used to configure the PHY during initialization

Default value: [10BASE Half-Duplex, 10BASE Full-Duplex, 100BASE Half-Duplex, 100BASE Full-Duplex, 1000BASE Half-Duplex, 1000BASE Full-Duplex]

Legal values: 10BASE Half-Duplex, 10BASE Full-Duplex, 100BASE Half-Duplex, 100BASE Full-Duplex, 1000BASE Half-Duplex, 1000BASE Full-Duplex