xlnx,gem
Description
Xilinx GEM Ethernet controller
Properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
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Specifies a reference to a node representing a PHY device.
This property is required. |
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Specifies the base clock frequency from which the GEM's TX clock
frequency will be derived using two dividers in the respective GEM's
clock control register in the CRL_APB. The GEM's TX clock frequency
is determined by the current link speed reported by the PHY, to
which it will be adjusted at run-time. Therefore, the value of this
item must be set to the clock frequency of the PLL supplying the
respective GEM's TX clock - by default, this is the IO PLL.
This property is required. |
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Moves the handling of the frame received interrupt including the
transfer of packet data from the DMA to network packet buffers and
the subsequent propagation of the received packets to the network
stack into the context of the ISR. Due to the unpredictability of
the runtime of the ISR whenever large amounts of data are received,
handling of the RX interrupt is normally deferred to the context
of the system work queue.
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Moves the handling of the frame transmission done interrupt into the
context of the system work queue. By default, TX done handling is per-
formed in the context of the ISR, as it only involves a limited number
of memory accesses. This option CAN NOT be used if any component ex-
ists within the current system setup that triggers the transmission
of packets from within the context of the system work queue!
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AMBA AHB burst length for DMA operations.
This property is required. Legal values: |
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Hardware RX buffer size, scalable between 1 kB and 8 kB, where the full
8 kB should be the default.
This property is required. Legal values: |
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Data offset in the hardware RX packet buffer (in bytes). Valid range is
0-3 bytes.
This property is required. |
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When set, the hardware TX data buffer will make use of the full 4 kB
that are available. If unset, the hardware TX data buffer will be
limited to 2 kB.
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The number of descriptors to be allocated in the RX buffer descriptor
ring. Must be <= 255.
This property is required. |
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The size of each receive data buffer, must be a multiple of 8, highest
valid value is 16320, values less than 64 are not really useful.
This property is required. |
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The number of descriptors to be allocated in the TX buffer descriptor
ring. Must be <= 255.
This property is required. |
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The size of each transmit data buffer, highest valid value is 16380,
values less than 64 are not really useful.
This property is required. |
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Optional feature flag - Ignore IPG rx_er. When set, rx_er has no
effect on the GEM's operation when rx_dv is low. Set this when using
the RGMII wrapper in half-duplex mode.
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Optional feature flag - Receive bad preamble. When set, frames with
non-standard preamble will not be rejected.
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Optional feature flag - Enable IPG stretch. When set, the transmit
IPG can be increased above 96 bit times depending on the previous
frame length using the IPG stretch register.
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Optional feature flag - Enable SGMII mode. Changes the behaviour of
the auto-negotiation advertisement and link partner ability registers
to meet the requirements of SGMII and reduces the duration of the link
timer from 10 ms to 1.6 ms.
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Optional feature flag - Disable rejection of FCS/CRC errors.
When set, frames with FCS/CRC errors will not be rejected. FCS error
statistics will still be collected for frames with bad FCS and FCS
status will be recorded in the frame's DMA descriptor. This option
should not be activated for normal operation.
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Optional feature flag - Enable frames to be received in half-duplex
mode while transmitting.
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Disable RX IPv4/IPv6/TCP/UDP checksum offload to hardware. Checksum
offloading is enabled by default, and automatically disabled for
QEMU targets, where hardware checksum offloading is not emulated,
without having to set this flag explicitly.
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Disable TX IPv4/IPv6/TCP/UDP checksum offload to hardware. Checksum
offloading is enabled by default, and automatically disabled for
QEMU targets, where hardware checksum offloading is not emulated,
without having to set this flag explicitly.
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Optional feature flag - Do not copy received pause frames to memory.
Set this option in order to prevent valid pause frames from being
copied to memory. When set, pause frames are not copied to memory
regardless of the state of the copy all frames bit, whether a hash
match is found or whether a type ID match is identified. If a desti-
nation address match is found the pause frame will be copied to
memory. Note that valid pause frames received will still increment
pause statistics and pause the transmission of frames as required.
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Optional feature flag - Remove FCS of received frames.
When set, received frames will be written to memory without their
frame check sequence (last 4 bytes). The frame length indicated will
be reduced by four bytes in this mode.
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Optional feature flag - Discard frames with length field errors.
When set, frames with a measured length shorter than the extracted
length field (as indicated by bytes 13 and 14 in a non-VLAN tagged
frame) will be discarded. This only applies to frames with a length
field less than 0x0600.
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Optional feature flag - Enable pause. When set, transmission will
pause if a non zero 802.3 classic pause frame is received and PFC
has not been negotiated.
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Optional feature flag - Enable TBI. When set, the TBI interface is en-
bled instead of the GMII/MII interface.
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Optional feature flag - Enable external address match. When set, the
external address match interface can be used to copy frames to memory.
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Optional feature flag - Enable reception of 1536 byte frames.
Normally, the GEM rejects any frame above 1518 bytes.
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Optional feature flag - Enable unicast hash. When set, unicast frames
will be accepted when the 6 bit hash function of the destination
address points to a bit that is set in the hash register.
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Optional feature flag - Enable multicast hash. When set, multicast
frames will be accepted when the 6 bit hash function of the desti-
nation address points to a bit that is set in the hash register.
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Optional feature flag - Reject broadcast frames. When set, frames
addressed to the all-ones broadcast address will be rejected.
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Optional feature flag - Discard non-VLAN frames. When set, only VLAN tagged frames will be passed to the address matching logic.
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Optional feature flag - Discard received packets when no AHB resource
is available.
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Optional feature flag - Enable AHB packet data endianness swap to big
endian. If this flag is not set, data will be little endian.
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Optional feature flag - Enable AHB management descriptor data endian-
ness swap to big endian. If this flag is not set, data will be little
endian.
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Specifies the MAC address that was assigned to the network device
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Use a random MAC address generated when the driver is initialized.
Note that using this choice and rebooting a board may leave stale
MAC address in peers' ARP caches and lead to issues and delays in
communication. (Use "ip neigh flush all" on Linux peers to clear
ARP cache.)
It is driver specific how the OUI octets are handled.
If set we ignore any setting of the local-mac-address property.
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A statically assigned MAC address prefix.
Can be combined with zephyr,random-mac-address or an NVMEM cell, for
example to set the OUI.
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Specifies the interface connection type between ethernet MAC and PHY.
Legal values: |
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Corresponding ptp clock device.
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Names for each nvmem-cells specified.
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List of phandles to the nvmem data cells.
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Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “xlnx,gem” compatible.
Name |
Type |
Details |
|---|---|---|
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Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
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This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
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Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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Indicates that the device is capable of coherent DMA operations.
For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
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HW spinlock id relevant to the device.
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Optional names given to the hwlock specifiers in the "hwlocks" property.
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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