microchip,xec-i2c-v2

Description

These nodes are “i2c” bus nodes.

Microchip I2C/SMB V2 controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

port-sel

int

soc block mapping to pin

This property is required.

pcr-scr

int

Encoded PCR index and bit position used for peripheral sleep enable
and reset.

This property is required.

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.

This property is required.

sda-gpios

phandle-array

I2C controller versions older than v3.8 do not make pin
state monitoring visible in the bit-bang register without
switching the pins from I2C control to bit-bang control.
This can cause disruption of an open I2C session. For older
hardware access pin state using the GPIO driver.

This property is required.

scl-gpios

phandle-array

Refer to the description of sda-gpios.

This property is required.

clock-frequency

int

Initial clock frequency in Hz

sq-size

int

Size of the submission queue for blocking requests

Default value: 4

cq-size

int

Size of the completion queue for blocking requests

Default value: 4

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.

girqs

array

Many DEC/MEC periperals interrupt signals are direct capable. The signals are
connected to bits in a GIRQ. Each GIRQ is composed of 5 32-bit registers:
status(latched or r/w1-c), set-enable, clr-enable, and result (read-only).
The read-only result register bits are the bitwise AND of status and enable.
Direct mode routes the individual result register bits to NVIC inputs. If
direct mode is disable by setting direct mode bit to 0 in the EC subsystem
interrupt control register then the result register outputs are OR'd together
and the OR'd result is connected to an NVIC input based on GIRQ number.
To enable an interrupt a driver must know:
a. NVIC input number and priority from the interrupts property
b. GIRQ number and bit position from the girqs property
The number of entries in interrupts and girqs should be the same in a DT node.

This property is required.