ite,it51xxx-i3cm

Vendor: ITE Tech. Inc.

Note

An implementation of a driver matching this compatible is available in drivers/i3c/i3cm_it51xxx.c.

Description

These nodes are “[‘i3c’, ‘i2c’]” bus nodes.

IT51XXX I3CM controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

io-channel

int

The it51xxx chip features four i3c io channels and two i3c cotroller
(i3cm) engines. This property allows the i3cm engine to select the
desired i3c io channel. To ensure proper i3c functionality, make sure
that multiple controllers (including the i3cm controller and i3cs
target engines) are not assigned the same io channel.

This property is required.

Legal values: 0, 1, 2, 3

i3c-pp-duty-cycle

int

The duty cycle of push-pull frequency(unit in percentage).

Default value: 50

i3c-od-scl-hz

int

The open-drain frequency for the i3c controller.

This property is required.

i3c-scl-hddat

int

i3c data hold time(0 by default). The time is calculated as:
t_hddat = (i3c-scl-hddat + 1) * 20.8ns. The range of i3c-scl-hddat is
[63:0].

i3c-scl-tcas

int

i3c clock after start condition(1 by default). The time is calculated as:
t_cas = (i3c-scl-tcas + 1) * 20.8ns. The maximum value is 255.

i3c-scl-tcbs

int

i3c clock before stop condition(0 by default). The time is calculated as:
t_cbs = (i3c-scl-tcbs + 1) * 20.8ns. The maximum value is 255.

i3c-scl-tcasr

int

i3c clock after repeated start condition(1 by default). The time is
calculated as: t_casr = (i3c-scl-tcasr + 1) * 20.8ns. The maximum value
is 255.

i3c-scl-tcbsr

int

i3c clock before repeated start condition(0 by default). The time is
calculated as: t_cbsr = (i3c-scl-tcbsr + 1) * 20.8ns. The maximum value
is 255.

i2c-scl-hddat

int

i2c data hold time(0 by default). The time is calculated as:
t_hddat = (i2c-scl-hddat + 1) * 20.8ns. The range of i3c-scl-hddat is
[65535:0].

i3c-scl-hz

int

Frequency of the SCL signal used for I3C transfers. When undefined,
use the controller default or as specified by the I3C specification.

i2c-scl-hz

int

Frequency of the SCL signal used for I2C transfers. When undefined
and there are I2C devices attached to the bus, look at the Legacy
Virtual Register (LVR) of all connected I2C devices to determine
the maximum allowed frequency.

primary-controller-da

int

This is the self assigned dynamic address of the I3C controller. This
is the address is used to communicate with itself after a handoff by
a secondary controller. This is only used if the controller is a primary
controller.

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.