microchip,xec-i3c
Description
These nodes are “[‘i3c’, ‘i2c’]” bus nodes.
Microchip XEC I3C controller.
The MEC SoCs integrate the Synopsys DesignWare DWC_mipi_i3c IP behind an
XEC-specific wrapper, so this binding shares the i3c_dw.c driver with
snps,designware-i3c. The wrapper adds a HOST_CFG port-select register, and
routes the interrupt through the XEC Interrupt Aggregator (ECIA)
Properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
|
I3C port selection written to HOST_CFG[2:0]. Selects which SoC pad group
the controller drives. Must agree with the pinctrl-0 pin group.
Default value: |
|
|
Frequency of the SCL signal used for I3C transfers. When undefined,
use the controller default or as specified by the I3C specification.
|
|
|
Frequency of the SCL signal used for I2C transfers. When undefined
and there are I2C devices attached to the bus, look at the Legacy
Virtual Register (LVR) of all connected I2C devices to determine
the maximum allowed frequency.
|
|
|
This is the self assigned dynamic address of the I3C controller. This
is the address is used to communicate with itself after a handoff by
a secondary controller. This is only used if the controller is a primary
controller.
|
|
|
Minimum high clock pulse length (ns) in Open-Drain mode for pure bus.
The default value is from Section 4.3.11.2 & Table 49 of the I3C
Basic Specification v1.2 (16-Dec-2024).
Default value: |
|
|
Minimum low clock pulse length (ns) in Open-Drain mode.
The default value is from Section 4.3.11.2 & Table 49 of the I3C
Basic Specification v1.2 (16-Dec-2024).
Default value: |
|
|
If true, the I3C bus initialization (i3c_bus_init) will not be
performed during driver initialization. This allows the application
to perform bus initialization at a later time.
|
|
|
If true, Hot-Join ACKs will not be enabled at the end of bus
initialization. Hot-Join events will be NACKed until the
application explicitly enables them.
|
|
|
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.
|
|
|
Pin configuration/s for the second state. See pinctrl-0.
|
|
|
Pin configuration/s for the third state. See pinctrl-0.
|
|
|
Pin configuration/s for the fourth state. See pinctrl-0.
|
|
|
Pin configuration/s for the fifth state. See pinctrl-0.
|
|
|
Names for the provided states. The number of names needs to match the
number of states.
|
|
|
Many DEC/MEC periperals interrupt signals are direct capable. The signals are
connected to bits in a GIRQ. Each GIRQ is composed of 5 32-bit registers:
status(latched or r/w1-c), set-enable, clr-enable, and result (read-only).
The read-only result register bits are the bitwise AND of status and enable.
Direct mode routes the individual result register bits to NVIC inputs. If
direct mode is disable by setting direct mode bit to 0 in the EC subsystem
interrupt control register then the result register outputs are OR'd together
and the OR'd result is connected to an NVIC input based on GIRQ number.
To enable an interrupt a driver must know:
a. NVIC input number and priority from the interrupts property
b. GIRQ number and bit position from the girqs property
The number of entries in interrupts and girqs should be the same in a DT node.
This property is required. |
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “microchip,xec-i3c” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
PCR clock specifier: <&pcr regidx bitpos MCHP_XEC_PCR_CLK_I3C>.
regidx and bitpos locate this controller's bit in the PCR sleep-enable /
clock-required / reset-enable registers. The clock ID selects the 192 MHz
I3C domain reported by the XEC clock control driver, which requires a SoC
that selects HAS_MCHP_MEC_I3C.
This property is required. |
|
|
This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
This property is required. Constant value: |
|
|
This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
This property is required. Constant value: |
|
|
Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
|
|
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
|
|
|
Information used to define a mapping (or translation) between the address
space of a bus (the "child address space") and the address space of the
bus node's parent (the "parent address space").
The "ranges" property is typically empty, or a sequence of triplets
(child bus address, parent bus address, length).
If the "ranges" property is empty, it specifies that the parent and child
address spaces are identical and no address translation is required.
If the "ranges" property is not present in a bus node, it is assumed that
no mapping exists between children of the node and the parent address space.
For details, see "2.3.8 ranges" in Devicetree Specification v0.4.
|
|
|
Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
|
|
Optional names given to each clock provider in the "clocks" property.
|
|
|
Indicates that the device is capable of coherent DMA operations.
For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
|
|
|
DMA channel specifiers relevant to the device.
|
|
|
Optional names given to the DMA channel specifiers in the "dmas" property.
|
|
|
IO channel specifiers relevant to the device.
|
|
|
Optional names given to the IO channel specifiers in the "io-channels" property.
|
|
|
Mailbox / IPM channel specifiers relevant to the device.
|
|
|
Optional names given to the mbox specifiers in the "mboxes" property.
|
|
|
Power domain specifiers relevant to the device.
|
|
|
Optional names given to the power domain specifiers in the "power-domains" property.
|
|
|
Number of cells in power-domains property
|
|
|
HW spinlock id relevant to the device.
|
|
|
Optional names given to the hwlock specifiers in the "hwlocks" property.
|
|
|
Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
|
|
|
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
|
|
Automatically configure the device for runtime power management after the
init function runs.
|
|
|
List of power states that will disable this device power.
|