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nxp,mcux-i3c

Vendor: NXP Semiconductors

Description

These nodes are “[‘i3c’, ‘i2c’]” bus nodes.

NXP MCUX I3C controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

i3c-od-scl-hz

int

Open Drain Frequency for the I3C controller. When undefined, use
the controller default or as specified by the I3C specification.

clk-divider

int

Main clock divider for I3C

This property is required.

clk-divider-tc

int

TC clock divider for I3C

This property is required.

clk-divider-slow

int

Slow clock divider for I3C

This property is required.

disable-open-drain-high-pp

boolean

If false, open drain high time is 1 PPBAUD count,
which is short high and long low.
If true, open drain high time is same as ODBAUD
so that open drain clock is 50% duty cycle.
Default is false.

i3c-scl-hz

int

Frequency of the SCL signal used for I3C transfers. When undefined,
use the controller default or as specified by the I3C specification.

i2c-scl-hz

int

Frequency of the SCL signal used for I2C transfers. When undefined
and there are I2C devices attached to the bus, look at the Legacy
Virtual Register (LVR) of all connected I2C devices to determine
the maximum allowed frequency.

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.