brcm,bcm2836-l1-intc

Description

BCM2836 / BCM2710 ARM-local interrupt controller (Pi 2 / Pi 3 / Pi Zero 2 W).

Sits at physical 0x40000000, ABOVE the peripheral base. Routes per-core
ARM generic timer IRQs, four mailbox IRQs per core (used as IPIs), the
per-core PMU IRQ, and the cascaded GPU IRQ -- the latter aggregating
every pending source on the BCM2835 ARMC peripheral interrupt
controller for whichever core the firmware (or Zephyr) routes the GPU
IRQ to.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

interrupt-controller

boolean

Convey's this node is an interrupt controller

This property is required.

#interrupt-cells

int

Cell 0: per-core source.
  0=CNTPSIRQ (secure phys), 1=CNTPNSIRQ (nonsec phys),
  2=CNTHPIRQ (hyp phys),    3=CNTVIRQ   (virtual),
  4..7=MAILBOX0..3,         8=GPU IRQ,  9=PMU.
Cell 1: trigger-type flags (IRQ_TYPE_LEVEL / IRQ_TYPE_EDGE).
Cell 2: priority -- unused by this controller (no per-IRQ
        priority register exists), kept as a fixed third cell
        so that the canonical ARM-arch-timer driver's
        DT_IRQ_BY_IDX(node, n, priority) macro resolves.

This property is required.

Constant value: 3

Specifier cell names

  • interrupt cells: irq, flags, priority