nxp,sramc

Description

NXP AHB SRAM Controller (SRAMC).

Controller for an external asynchronous parallel SRAM (or SRAM-like FPGA)
interface. The SRAMCR0/SRAMCR1 configuration registers physically reside in
the BLK_CTRL_WAKEUPMIX block, so this node references that block through the
"nxp,blk-ctrl" phandle instead of mapping the same registers with its own
"reg" (the BLK_CTRL_WAKEUPMIX block is already described by the
"nxp,imx-blkctrl-wakeup" node).

Each chip-select (up to 4, each up to 128 KB) that carries an external SRAM
is described as an "mmio-sram" child node whose "reg" is the CS memory window
(e.g. CS0 at 0x43880000 on i.MX RT118x). Example:

  sramc: sramc {
      compatible = "nxp,sramc";
      nxp,blk-ctrl = <&blkctrl_wakeup>;
      pinctrl-0 = <&pinmux_sramc>;
      pinctrl-names = "default";
      port-size = "16-bit";
      address-mode = "admux";
      #address-cells = <1>;
      #size-cells = <1>;
      status = "okay";

      ext_sram: sram@43880000 {
          compatible = "mmio-sram";
          reg = <0x43880000 DT_SIZE_K(128)>;
      };
  };

Properties

Properties not inherited from the base binding file.

Name

Type

Details

nxp,blk-ctrl

phandle

 
Reference to the BLK_CTRL_WAKEUPMIX block node that hosts the SRAMCR0 and
SRAMCR1 configuration registers. The driver takes the controller base
address from this referenced node.

This property is required.

turnaround-time

int

 
Turnaround time TA. Actual = (TA+1) * granularity.

Default value: 1

Value range: 0 to 15

address-hold-time

int

 
Address hold time AH. Actual = (AH+1) * granularity.

Default value: 1

Value range: 0 to 15

address-setup-time

int

 
Address setup time AS. Actual = AS * granularity.

Default value: 4

Value range: 0 to 15

ce-hold-time

int

 
Chip-enable hold time CEH. Actual = CEH * granularity.

Default value: 1

Value range: 0 to 15

ce-setup-time

int

 
Chip-enable setup time CES. Actual = CES * granularity.

Default value: 1

Value range: 0 to 15

adv-polarity

string

 
ADV# signal polarity.

Default value: active-low

Legal values: active-low, active-high

address-mode

string

 
SRAM address mode.

Default value: admux

Legal values: admux, non-admux

port-size

string

 
External SRAM data-port width. This is board/part specific and must be
set explicitly: an 8-bit device left at a wider default would be driven
with the wrong bus width, so no default is provided.

This property is required.

Legal values: 8-bit, 16-bit

bus-timeout-enable

boolean

 
Enable AHB bus timeout (BTOEN).

bus-timeout-counter

int

 
AHB bus timeout wait cycles BTO. Timeout = BTO * 1024 hclk.

Default value: 0

Value range: 0 to 255

prescaler

string

 
Prescaler that sets the timing granularity.

Default value: prescaler-4

Legal values: prescaler-1, prescaler-2, prescaler-3, prescaler-4

read-enable-high-time

int

 
Read-enable (OE#) high time REH. Actual = (REH+1) * granularity.

Default value: 9

Value range: 0 to 15

read-enable-low-time

int

 
Read-enable (OE#) low time REL. Actual = (REL+1) * granularity.

Default value: 16

Value range: 0 to 63

write-enable-high-time

int

 
Write-enable (WE#) high time WEH. Actual = (WEH+1) * granularity.

Default value: 10

Value range: 0 to 15

write-enable-low-time

int

 
Write-enable (WE#) low time WEL. Actual = (WEL+1) * granularity.

Default value: 31

Value range: 0 to 63

pinctrl-0

phandles

 
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.