infineon,hppass-analog

Description

Infineon HPPASS (High Performance Programmable Analog Sub-System)
Multi-Function Device.

The HPPASS subsystem contains multiple analog peripherals (SAR ADC, CSG)
coordinated by an Autonomous Controller (AC) state machine.  This MFD
device manages the shared resources: subsystem initialisation, AC lifecycle,
STT management, and the combined MCPASS interrupt (AC state + error
conditions).

Individual peripherals (SAR ADC, CSG) are represented as child nodes of this device
and own their individual interrupt lines.

Examples

#include <dt-bindings/mfd/infineon-hppass.h>

/* Basic mode: no ac-states property.
 * Driver auto-generates 2-state SAR startup sequence.
 */
&hppass_analog0 {
    status = "okay";
    /* SAR child auto-detected, no AC config needed */
};

#include <dt-bindings/mfd/infineon-hppass.h>

/*
 * Advanced mode: custom 3-state sequence.
 * State 0: Wait for blocks ready, enable SAR
 * State 1: Trigger SAR group 0, wait for done, loop to 1
 * State 2: Stop
 */

/ {
    hppass_state0: hppass-ac-state-0 {
        compatible = "infineon,hppass-ac-state";
        ac-condition = <IFX_HPPASS_AC_COND_BLOCK_READY>;
        ac-action = <IFX_HPPASS_AC_ACTION_WAIT_FOR>;
        sar-unlock = <1>;
        sar-enable = <1>;
    };

    hppass_state1: hppass-ac-state-1 {
        compatible = "infineon,hppass-ac-state";
        ac-condition = <IFX_HPPASS_AC_COND_SAR_GROUP_0_DONE>;
        ac-action = <IFX_HPPASS_AC_ACTION_WAIT_FOR>;
        branch-state-idx = <1>;
        sar-unlock = <1>;
        sar-enable = <1>;
        sar-grp-msk = <IFX_HPPASS_SAR_GRP_0>;
    };

    hppass_state2: hppass-ac-state-2 {
        compatible = "infineon,hppass-ac-state";
        ac-condition = <IFX_HPPASS_AC_COND_FALSE>;
        ac-action = <IFX_HPPASS_AC_ACTION_STOP>;
    };
};

&hppass_analog0 {
    ac-states = <&hppass_state0 &hppass_state1 &hppass_state2>;
    startup-clk-div = <4>;
    trig-in-0-type = <IFX_HPPASS_TR_FW_PULSE>;
};

Properties

Properties not inherited from the base binding file.

Name	Type	Details
`ac-states`	`phandles`	Ordered list of AC state node phandles for advanced mode. When present, the driver uses these nodes to build the full State Transition Table. Each referenced node must have compatible "infineon,hppass-ac-state". When omitted, the driver uses a built-in 2-state startup sequence (basic mode) and automatically populates SAR/CSG fields based on child node status.
`ac-gpio-out-en-msk`	`int`	AC GPIO output enable mask. Use IFX_HPPASS_GPIO_OUT_* constants from <dt-bindings/mfd/infineon-hppass.h>. Enables GPIO outputs for AC state machine control. Default value: `0`
`startup-clk-div`	`int`	Startup clock divider (1-256). Divides the HPPASS clock for the startup sequencer. Default value: `1`
`startup-0-count`	`int`	Startup phase 0 count in HPPASS clock cycles (0-255). Actual is count + 1. Default value: `0`
`startup-0-sar`	`int`	Startup phase 0 SAR enable flag (0 or 1). Default value: `0`
`startup-0-csg-chan`	`int`	Startup phase 0 CSG channel enable flag (0 or 1). Default value: `0`
`startup-0-csg-slice`	`int`	Startup phase 0 CSG slice enable flag (0 or 1). Default value: `0`
`startup-0-csg-ready`	`int`	Startup phase 0 CSG auto-zero/comparator gate enable flag (0 or 1). Default value: `0`
`startup-1-count`	`int`	Startup phase 1 count in HPPASS clock cycles (0-255). Default value: `0`
`startup-1-sar`	`int`	Startup phase 1 SAR enable flag (0 or 1). Default value: `0`
`startup-1-csg-chan`	`int`	Startup phase 1 CSG channel enable flag (0 or 1). Default value: `0`
`startup-1-csg-slice`	`int`	Startup phase 1 CSG slice enable flag (0 or 1). Default value: `0`
`startup-1-csg-ready`	`int`	Startup phase 1 CSG auto-zero/comparator gate enable flag (0 or 1). Default value: `0`
`startup-2-count`	`int`	Startup phase 2 count in HPPASS clock cycles (0-255). Default value: `0`
`startup-2-sar`	`int`	Startup phase 2 SAR enable flag (0 or 1). Default value: `0`
`startup-2-csg-chan`	`int`	Startup phase 2 CSG channel enable flag (0 or 1). Default value: `0`
`startup-2-csg-slice`	`int`	Startup phase 2 CSG slice enable flag (0 or 1). Default value: `0`
`startup-2-csg-ready`	`int`	Startup phase 2 CSG auto-zero/comparator gate enable flag (0 or 1). Default value: `0`
`startup-3-count`	`int`	Startup phase 3 count in HPPASS clock cycles (0-255). Default value: `0`
`startup-3-sar`	`int`	Startup phase 3 SAR enable flag (0 or 1). Default value: `0`
`startup-3-csg-chan`	`int`	Startup phase 3 CSG channel enable flag (0 or 1). Default value: `0`
`startup-3-csg-slice`	`int`	Startup phase 3 CSG slice enable flag (0 or 1). Default value: `0`
`startup-3-csg-ready`	`int`	Startup phase 3 CSG auto-zero/comparator gate enable flag (0 or 1). Default value: `0`
`trig-in-0-type`	`int`	Trigger input 0 type. Use IFX_HPPASS_TR_* constants. Default: DISABLED (0). Default value: `0`
`trig-in-0-hw-mode`	`int`	Trigger input 0 HW mode. Use IFX_HPPASS_TR_HW_* constants. Only effective when trig-in-0-type is HW_A or HW_B. Default value: `0`
`trig-in-1-type`	`int`	Trigger input 1 type. Use IFX_HPPASS_TR_* constants. Default value: `0`
`trig-in-1-hw-mode`	`int`	Trigger input 1 HW mode. Use IFX_HPPASS_TR_HW_* constants. Default value: `0`
`trig-in-2-type`	`int`	Trigger input 2 type. Use IFX_HPPASS_TR_* constants. Default value: `0`
`trig-in-2-hw-mode`	`int`	Trigger input 2 HW mode. Use IFX_HPPASS_TR_HW_* constants. Default value: `0`
`trig-in-3-type`	`int`	Trigger input 3 type. Use IFX_HPPASS_TR_* constants. Default value: `0`
`trig-in-3-hw-mode`	`int`	Trigger input 3 HW mode. Use IFX_HPPASS_TR_HW_* constants. Default value: `0`
`trig-in-4-type`	`int`	Trigger input 4 type. Use IFX_HPPASS_TR_* constants. Default value: `0`
`trig-in-4-hw-mode`	`int`	Trigger input 4 HW mode. Use IFX_HPPASS_TR_HW_* constants. Default value: `0`
`trig-in-5-type`	`int`	Trigger input 5 type. Use IFX_HPPASS_TR_* constants. Default value: `0`
`trig-in-5-hw-mode`	`int`	Trigger input 5 HW mode. Use IFX_HPPASS_TR_HW_* constants. Default value: `0`
`trig-in-6-type`	`int`	Trigger input 6 type. Use IFX_HPPASS_TR_* constants. Default value: `0`
`trig-in-6-hw-mode`	`int`	Trigger input 6 HW mode. Use IFX_HPPASS_TR_HW_* constants. Default value: `0`
`trig-in-7-type`	`int`	Trigger input 7 type. Use IFX_HPPASS_TR_* constants. Default value: `0`
`trig-in-7-hw-mode`	`int`	Trigger input 7 HW mode. Use IFX_HPPASS_TR_HW_* constants. Default value: `0`
`trig-pulse-0`	`int`	Trigger output 0 pulse source. Use IFX_HPPASS_TR_OUT_* constants. Default: DISABLED (0). Default value: `0`
`trig-pulse-1`	`int`	Trigger output 1 pulse source. Use IFX_HPPASS_TR_OUT_* constants. Default value: `0`
`trig-pulse-2`	`int`	Trigger output 2 pulse source. Use IFX_HPPASS_TR_OUT_* constants. Default value: `0`
`trig-pulse-3`	`int`	Trigger output 3 pulse source. Use IFX_HPPASS_TR_OUT_* constants. Default value: `0`
`trig-pulse-4`	`int`	Trigger output 4 pulse source. Use IFX_HPPASS_TR_OUT_* constants. Default value: `0`
`trig-pulse-5`	`int`	Trigger output 5 pulse source. Use IFX_HPPASS_TR_OUT_* constants. Default value: `0`
`trig-pulse-6`	`int`	Trigger output 6 pulse source. Use IFX_HPPASS_TR_OUT_* constants. Default value: `0`
`trig-pulse-7`	`int`	Trigger output 7 pulse source. Use IFX_HPPASS_TR_OUT_* constants. Default value: `0`
`trig-level-0-sync-bypass`	`int`	Trigger output level 0 sync bypass flag (0 or 1). Default value: `0`
`trig-level-0-comp-msk`	`int`	Trigger output level 0 CSG comparator mask (5 bits, one per CSG slice). Default value: `0`
`trig-level-0-limit-msk`	`int`	Trigger output level 0 SAR limit detector mask (8 bits). Default value: `0`
`trig-level-1-sync-bypass`	`int`	Trigger output level 1 sync bypass flag (0 or 1). Default value: `0`
`trig-level-1-comp-msk`	`int`	Trigger output level 1 CSG comparator mask. Default value: `0`
`trig-level-1-limit-msk`	`int`	Trigger output level 1 SAR limit detector mask. Default value: `0`
`trig-level-2-sync-bypass`	`int`	Trigger output level 2 sync bypass flag (0 or 1). Default value: `0`
`trig-level-2-comp-msk`	`int`	Trigger output level 2 CSG comparator mask. Default value: `0`
`trig-level-2-limit-msk`	`int`	Trigger output level 2 SAR limit detector mask. Default value: `0`
`trig-level-3-sync-bypass`	`int`	Trigger output level 3 sync bypass flag (0 or 1). Default value: `0`
`trig-level-3-comp-msk`	`int`	Trigger output level 3 CSG comparator mask. Default value: `0`
`trig-level-3-limit-msk`	`int`	Trigger output level 3 SAR limit detector mask. Default value: `0`
`trig-level-4-sync-bypass`	`int`	Trigger output level 4 sync bypass flag (0 or 1). Default value: `0`
`trig-level-4-comp-msk`	`int`	Trigger output level 4 CSG comparator mask. Default value: `0`
`trig-level-4-limit-msk`	`int`	Trigger output level 4 SAR limit detector mask. Default value: `0`
`trig-level-5-sync-bypass`	`int`	Trigger output level 5 sync bypass flag (0 or 1). Default value: `0`
`trig-level-5-comp-msk`	`int`	Trigger output level 5 CSG comparator mask. Default value: `0`
`trig-level-5-limit-msk`	`int`	Trigger output level 5 SAR limit detector mask. Default value: `0`
`trig-level-6-sync-bypass`	`int`	Trigger output level 6 sync bypass flag (0 or 1). Default value: `0`
`trig-level-6-comp-msk`	`int`	Trigger output level 6 CSG comparator mask. Default value: `0`
`trig-level-6-limit-msk`	`int`	Trigger output level 6 SAR limit detector mask. Default value: `0`
`trig-level-7-sync-bypass`	`int`	Trigger output level 7 sync bypass flag (0 or 1). Default value: `0`
`trig-level-7-comp-msk`	`int`	Trigger output level 7 CSG comparator mask. Default value: `0`
`trig-level-7-limit-msk`	`int`	Trigger output level 7 SAR limit detector mask. Default value: `0`

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “infineon,hppass-analog” compatible.

Name	Type	Details
`reg`	`array`	Information used to address the device. The value is specific to the device (i.e. is different depending on the compatible property). The "reg" property is typically a sequence of (address, length) pairs. Each pair is called a "register block". Values are conventionally written in hex. For details, see "2.3.6 reg" in Devicetree Specification v0.4. This property is required. See Important properties for more information.
`interrupts`	`array`	Combined MCPASS interrupt (AC state transitions and error conditions). This property is required. See Important properties for more information.
`#address-cells`	`int`	This property encodes the number of <u32> cells used by address fields in "reg" properties in this node's children. For details, see "2.3.5 #address-cells and #size-cells" in Devicetree Specification v0.4. Constant value: `1`
`#size-cells`	`int`	This property encodes the number of <u32> cells used by size fields in "reg" properties in this node's children. For details, see "2.3.5 #address-cells and #size-cells" in Devicetree Specification v0.4. Constant value: `1`
`status`	`string`	Indicates the operational status of the hardware or other resource that the node represents. In particular: - "okay" means the resource is operational and, for example, can be used by device drivers - "disabled" means the resource is not operational and the system should treat it as if it is not present For details, see "2.3.4 status" in Devicetree Specification v0.4. Legal values: `okay`, `disabled`, `reserved`, `fail`, `fail-sss` See Important properties for more information.
`compatible`	`string-array`	This property is a list of strings that essentially define what type of hardware or other resource this devicetree node represents. Each device driver checks for specific compatible property values to find the devicetree nodes that represent resources that the driver should manage. The recommended format is "vendor,device", The "vendor" part is an abbreviated name of the vendor. The "device" is usually from the datasheet. The compatible property can have multiple values, ordered from most- to least-specific. Having additional values is useful when the device is a specific instance of a more general family, to allow the system to match the most specific driver available. For details, see "2.3.1 compatible" in Devicetree Specification v0.4. This property is required. See Important properties for more information.
`reg-names`	`string-array`	Optional names given to each register block in the "reg" property. For example: / { soc { #address-cells = <1>; #size-cells = <1>; uart@1000 { reg = <0x1000 0x2000>, <0x3000 0x4000>; reg-names = "foo", "bar"; }; }; }; The uart@1000 node has two register blocks: - one with base address 0x1000, size 0x2000, and name "foo" - another with base address 0x3000, size 0x4000, and name "bar"
`interrupts-extended`	`compound`	Extended interrupt specifier for device, used as an alternative to the "interrupts" property. For details, see "2.4 Interrupts and Interrupt Mapping" in Devicetree Specification v0.4.
`interrupt-names`	`string-array`	Optional names given to each interrupt generated by a device. The interrupts themselves are defined in either "interrupts" or "interrupts-extended" properties. For details, see "2.4 Interrupts and Interrupt Mapping" in Devicetree Specification v0.4.
`interrupt-parent`	`phandle`	If present, this refers to the node which handles interrupts generated by this device. For details, see "2.4 Interrupts and Interrupt Mapping" in Devicetree Specification v0.4.
`label`	`string`	Human readable string describing the device. Use of this property is deprecated except as needed on a case-by-case basis. For details, see "4.1.2 Miscellaneous Properties" in Devicetree Specification v0.4. See Important properties for more information.
`clocks`	`phandle-array`	Information about the device's clock providers. In general, this property should follow conventions established in the dt-schema binding: https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
`clock-names`	`string-array`	Optional names given to each clock provider in the "clocks" property.
`dma-coherent`	`boolean`	Indicates that the device is capable of coherent DMA operations. For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
`dmas`	`phandle-array`	DMA channel specifiers relevant to the device.
`dma-names`	`string-array`	Optional names given to the DMA channel specifiers in the "dmas" property.
`io-channels`	`phandle-array`	IO channel specifiers relevant to the device.
`io-channel-names`	`string-array`	Optional names given to the IO channel specifiers in the "io-channels" property.
`mboxes`	`phandle-array`	Mailbox / IPM channel specifiers relevant to the device.
`mbox-names`	`string-array`	Optional names given to the mbox specifiers in the "mboxes" property.
`power-domains`	`phandle-array`	Power domain specifiers relevant to the device.
`power-domain-names`	`string-array`	Optional names given to the power domain specifiers in the "power-domains" property.
`#power-domain-cells`	`int`	Number of cells in power-domains property
`hwlocks`	`phandle-array`	HW spinlock id relevant to the device.
`hwlock-names`	`string-array`	Optional names given to the hwlock specifiers in the "hwlocks" property.
`zephyr,deferred-init`	`boolean`	Do not initialize device automatically on boot. Device should be manually initialized using device_init().
`wakeup-source`	`boolean`	Property to identify that a device can be used as wake up source. When this property is provided a specific flag is set into the device that tells the system that the device is capable of wake up the system. Wake up capable devices are disabled (interruptions will not wake up the system) by default but they can be enabled at runtime if necessary.
`zephyr,pm-device-runtime-auto`	`boolean`	Automatically configure the device for runtime power management after the init function runs.
`zephyr,disabling-power-states`	`phandles`	List of power states that will disable this device power.