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zephyr,swdp-gpio

Vendor: Zephyr-specific binding

Description

This is a representation of the Serial Wire Debug Port interface
implementation by GPIO bit-banging.

Schematic using dual-supply bus transceiver and separate dout and dnoe pins

       VCC_3V3                      VCC_REF
          ^                           ^
          |       +-------------+     |
          +-------|vcca     vccb|-----+
                  |             |
 clk-gpios -------|a           b|-------------- SWD CLK
                  |             |
 noe-gpios -------|dir       gnd|-----+
                  +-------------+     |
                   74LVC1T45          v
                                     GND


       VCC_3V3                      VCC_REF
          ^                           ^
          |       +-------------+     |
          +-------|vcca     vccb|-----+
                  |             |
 dio-gpios -------|a           b|------------*- SWD DIO
                  |             |            |
          +-------|dir       gnd|-----+      |
          |       +-------------+     |      |
          v        74LVC1T45          v      |
         GND                         GND     |
                                             |
                                             |
       VCC_3V3                      VCC_REF  |
          ^                           ^      |
          |       +-------------+     |      |
          +-------|vcca     vccb|-----+      |
                  |             |            |
dout-gpios -------|a           b|------------+
                  |             |
dnoe-gpios -------|dir       gnd|-----+
                  +-------------+     |
                   74LVC1T45          v
                                     GND

Direct connection using only dio pin for SWD DIO.

 clk-gpios ------------------------------------ SWD CLK

 dio-gpios ------------------------------------ SWD DIO

Of course, bidirectional bus transceiver between dio and SWD DIO can also be
used together with noe pin to enable/disable transceivers.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clk-gpios

phandle-array

GPIO pin used for SWCLK output

This property is required.

dio-gpios

phandle-array

GPIO pin used for SWDIO input. This pin is also used for the SWDIO output
if separate output pin is not defined.

This property is required.

dout-gpios

phandle-array

Optional GPIO pin used for SWDIO output.

dnoe-gpios

phandle-array

GPIO pin used to disable the SWDIO output buffer behind optional
pin dout-gpios.

noe-gpios

phandle-array

Optional pin to disable all bus transceivers if any are present.

reset-gpios

phandle-array

Optional GPIO pin used for RESET output.

port-write-cycles

int

Number of processor cycles for I/O Port write operations.For example, the
GPIO clock may be different from the CPU clock. This can usually be
found in the SoC documentation.

This property is required.