ambiq,mspi-device (on mspi bus)

Vendor: Ambiq Micro, Inc.

Description

Ambiq MSPI device

Properties

Properties not inherited from the base binding file.

Name

Type

Details

mspi-io-mode

string

 
MSPI I/O mode setting.
In device tree, it is normally the target io mode
after initialization.

This property is required.

Legal values: 'MSPI_IO_MODE_SINGLE', 'MSPI_IO_MODE_DUAL', 'MSPI_IO_MODE_DUAL_1_1_2', 'MSPI_IO_MODE_DUAL_1_2_2', 'MSPI_IO_MODE_QUAD', 'MSPI_IO_MODE_QUAD_1_1_4', 'MSPI_IO_MODE_QUAD_1_4_4', 'MSPI_IO_MODE_OCTAL', 'MSPI_IO_MODE_OCTAL_1_1_8', 'MSPI_IO_MODE_OCTAL_1_8_8', 'MSPI_IO_MODE_HEX', 'MSPI_IO_MODE_HEX_8_8_16', 'MSPI_IO_MODE_HEX_8_16_16'

mspi-data-rate

string

 
MSPI data rate setting. In device tree, it is normally the target data rate after initialization.

This property is required.

Legal values: 'MSPI_DATA_RATE_SINGLE', 'MSPI_DATA_RATE_S_S_D', 'MSPI_DATA_RATE_S_D_D', 'MSPI_DATA_RATE_DUAL'

mspi-hardware-ce-num

int

 
It can be only CE0 or CE1,
but there could be multiple of CE0 or CE1 for a controller

This property is required.

rx-dummy

int

 
The number of data or clock cycles between addr and data
in RX direction.
0 means the RX dummy phase is disabled.

This property is required.

tx-dummy

int

 
The number of data or clock cycles between addr and data
in TX direction.
0 means the TX dummy phase is disabled.

This property is required.

read-command

int

 
Read command to be sent in RX direction.

This property is required.

write-command

int

 
Write command to be sent in RX direction.

This property is required.

command-length

string

 
Length in bytes of the write and read commands.

This property is required.

Legal values: 'INSTR_DISABLED', 'INSTR_1_BYTE', 'INSTR_2_BYTE'

address-length

string

 
Length in bytes of address to be sent in address phase.

This property is required.

Legal values: 'ADDR_DISABLED', 'ADDR_1_BYTE', 'ADDR_2_BYTE', 'ADDR_3_BYTE', 'ADDR_4_BYTE'

ambiq,timing-config-mask

int

 
It must be defined in the board DTS based on Soc series.

This property is required.

ambiq,timing-config

array

 
Array of tuples to configure the timing parameters
default =
<
  .ui8WriteLatency   = 0,
  .ui8TurnAround     = 0,
  .bTxNeg            = false,
  .bRxNeg            = false,
  .bRxCap            = false,
  .ui32TxDQSDelay    = 0,
  .ui32RxDQSDelay    = 0,
  .ui32RXDQSDelayEXT = 0,
>

Default value: [0, 0, 0, 0, 0, 0, 0, 0]

mspi-max-frequency

int

 
Maximum clock frequency of device to configure in Hz.
In device tree, it is normally the target operating
frequency after initialization.

This property is required.

mspi-cpp-mode

string

 
MSPI clock polarity setting.
MSPI_CPP_MODE_0: CPOL=0, CPHA=0
MSPI_CPP_MODE_1: CPOL=0, CPHA=1
MSPI_CPP_MODE_2: CPOL=1, CPHA=0
MSPI_CPP_MODE_3: CPOL=1, CPHA=1

Legal values: 'MSPI_CPP_MODE_0', 'MSPI_CPP_MODE_1', 'MSPI_CPP_MODE_2', 'MSPI_CPP_MODE_3'

mspi-endian

string

 
MSPI transfer MSB or LSB first.

Legal values: 'MSPI_LITTLE_ENDIAN', 'MSPI_BIG_ENDIAN'

mspi-ce-polarity

string

 
MSPI CE polarity. In most cases, it is active low.

Legal values: 'MSPI_CE_ACTIVE_LOW', 'MSPI_CE_ACTIVE_HIGH'

mspi-dqs-enable

boolean

 
Enable DQS mode for a device which supports it.
This will be checked against dqs-support and configure
the MSPI hardware if it supports DQS mode.

mspi-hold-ce

boolean

 
In some cases, it is necessary for the controller to manage
MSPI chip enable (under software control), so that multiple
mspi transactions can be performed without releasing CE.
A typical use case is variable length MSPI packets where
the first mspi transaction reads the length and the second
mspi transaction reads length bytes.

xip-config

array

 
Array of parameters to configure the xip feature.
enable: whether XIP feature is enabled.
address_offset: The offset in bytes to the start of the
                platform specific XIP address region.
size: The size in bytes of the XIP address region one
      wish to enable or disable.
permission: The permission granted to the region. (RW/RO)

For controller that support this feature. One may map the device
memory into Soc system memory map. i.e. XIP address region
So that the device may be used as an external RAM and execute code.

default =
<
  .enable         = false;
  .address_offset = 0;
  .size           = 0;
  .permission     = 0;
>

scramble-config

array

 
Array of parameters to configure the scrambling feature.
enable: whether scrambling feature is enabled.
address_offset: The offset in bytes to the start address which
                can be the offset to the start of the platform
                specific XIP address region or phyiscal device address.

size: The size in bytes of the region one wish to enable or disable.
For controller that support hardware scrambling, one may use it for
additional security to protect data or code stored in external devices.

default =
<
  .enable         = false;
  .address_offset = 0;
  .size           = 0;
>

ce-break-config

array

 
Array of parameters to configure the auto CE break feature.
mem_boundary: Memory boundary in bytes of a device that a transfer
              should't cross.
time_to_break: The maximum time of a transfer should't exceed for
               a device in micro seconds(us).

This is typically used with devices that has memory boundaries or
requires periodic internal refresh. e.g. psram

default =
<
  .mem_boundary    = 0;
  .time_to_break   = 0;
>

supply-gpios

phandle-array

 
GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

 
Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

jedec-id

uint8-array

 
JEDEC ID as manufacturer ID, memory type, memory density

size

int

 
flash capacity in bits

sfdp-bfp

uint8-array

 
Contains the 32-bit words in little-endian byte order from the
JESD216 Serial Flash Discoverable Parameters Basic Flash
Parameters table.  This provides flash-specific configuration
information in cases were runtime retrieval of SFDP data
is not desired.

quad-enable-requirements

string

 
Quad Enable Requirements value from JESD216 BFP DW15.

Use NONE if the device detects 1-1-4 and 1-4-4 modes by the
instruction.  Use S1B6 if QE is bit 6 of the first status register
byte, and can be configured by reading then writing one byte with
RDSR and WRSR.  For other fields see the specification.

Legal values: 'NONE', 'S2B1v1', 'S1B6', 'S2B7', 'S2B1v4', 'S2B1v5', 'S2B1v6'

enter-4byte-addr

int

 
Enter 4-Byte Addressing value from JESD216 BFP DW16

This property is ignored if the device is configured to use SFDP data
from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read
SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).

For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24
of DW16 identifying ways a device can be placed into 4-byte addressing
mode.  If provided as a non-zero value the driver assumes that 4-byte
addressing is require to access the full address range, and
automatically puts the device into 4-byte address mode when the device
is initialized.

page-size

int

 
Number of bytes in a page from JESD216 BFP DW11

This property is only used in the CONFIG_SPI_NOR_SFDP_MINIMAL configuration.
It is ignored if the device is configured to use SFDP data
from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or
if the SFDP parameters are read from the device at
runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).

The default value is 256 bytes if the value is not specified.