bflb,sf-device
Description
Bouffalolab Serial Flash controller device
Bouffalolab Serial Flash controller device
Examples
// S3A1604 MRAM in QPI QIO
&sf_bank2 {
reg = <0xa4000000 0x200000>;
ranges = <0x0 0xa4000000 0x200000>;
status = "okay";
pinctrl-0 = <&sf3_default>;
pinctrl-names = "default";
s3a1604: mram@0 {
compatible = "bflb,sf-device";
reg = <0 0x200000>;
spi-bus-mode = <4>;
use-qpi;
sf-pad = <3>;
jedec-id = [d9 01 05];
read-command = <0x0b>;
read-dummy-cycles = <3>;
write-command = <0xda>;
write-dummy-cycles = <0>;
enter-qpi-command = <0x38>;
exit-qpi-command = <0xff>;
initialization-sequence = <0x06 0x0 0x0 0x87 0x01250600 0x4>;
quirk-bytes-read = [ a0 ];
quirk-bytes-write = [ a0 ];
};
};
// PM004MNI MRAM in QPI QIO
&sf_bank2 {
reg = <0xa4000000 0x80000>;
ranges = <0x0 0xa4000000 0x80000>;
status = "okay";
pinctrl-0 = <&sf2_default>;
pinctrl-names = "default";
pm004mni: mram@0 {
compatible = "bflb,sf-device";
reg = <0 0x80000>;
spi-bus-mode = <4>;
use-qpi;
sf-pad = <2>;
jedec-id = [29 55 00];
read-command = <0xeb>;
read-dummy-cycles = <0>;
write-command = <0x38>;
write-dummy-cycles = <0>;
enter-qpi-command = <0x35>;
exit-qpi-command = <0xf5>;
};
};
Properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
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Which pad is this device using. This is directly related to which pins are used.
Pad 1 is usually the embedded flash, Pad 2 and Pad 3 are usually external.
Main exception is BL70x/L where the default embedded pad is SF2.
External pads require a pinctrl entry at the bank.
This property is required. Legal values: |
|
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The width and mode of SPI bus to use for the device.
Numbers refer to the number of line used in each direction.
Possible values are:
- IO <0> = 1-1-1 mode
- DO <1> = 1-1-2 mode
- QO <2> = 1-1-4 mode
- DIO <3> = 1-2-2 mode
- QIO <4> = 1-4-4 mode or 4-4-4 mode (QPI), or 0-4-4 mode (Continuous Read / XIP mode)
This property is required. Legal values: |
|
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Enable QPI, only 4-4-4 is supported
|
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Some pads can be both external and internal (like SF2 on BL70x/L).
Use external pad instead of the internal one.
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SPI command to use for memory-mapped reading.
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Dummy cycles for automatic read mode.
They are expressed in bytes of the address: 8 cycles with NIO, DO, QO, 4 with DIO, 2 with QIO.
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Enable continuous read using this command setting.
|
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|
SPI command to use for memory-mapped writing. Device must not require explicit or page sized
erase.
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Dummy cycles for automatic write mode.
They are expressed in bytes of the address: 8 cycles with NIO, DO, QO, 4 with DIO, 2 with QIO.
|
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Triples of command, data, datalength writes to set things up at setup time.
For example to clear out block protection, or setup dummy timing.
up to 4 bytes of data can be sent at once.
Remember the byte order is inverted (right to left).
Example of setting OC bits to 11 and disabling block protections on MX25L25645G:
initialization-sequence = <0x06 0x0 0x0 0x1 0xc002 0x2>;
If using this on internal flash this can be VERY dangerous, devcube / eflash loader is able
to recover register settings in case of needs.
|
|
|
Command to enter QPI
|
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Command to exit QPI
|
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JEDEC ID as manufacturer ID, memory type, memory density.
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Flash Read delay. The default is appropriate for standard flash speed.
Default value: Legal values: |
|
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Invert Clock Signal.
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Invert RX Clock Signal.
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Up to 4 bytes appended after the address for the auto-write command.
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Up to 4 bytes appended after the address for the auto-read command.
|
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Fine tune pad delay for data in (0-3). Fine tuning is not usually necessary.
Default value: |
|
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Fine tune pad delay for data out (0-3). Fine tuning is not usually necessary.
Default value: |
|
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Fine tune pad delay for CS (0-3). Fine tuning is not usually necessary.
Default value: |
|
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Fine tune pad delay for CLK (0-3). Fine tuning is not usually necessary.
Default value: |
|
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Fine tune pad delay for output enable (0-3). Fine tuning is not usually necessary.
Default value: |
|
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address alignment required by flash erase operations
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address alignment required by flash write operations
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Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “bflb,sf-device” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
|
|
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
|
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
|
|
Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
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|
Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
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|
If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
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|
Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
|
|
Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
|
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
|
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Indicates that the device is capable of coherent DMA operations.
For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
|
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
|
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HW spinlock id relevant to the device.
|
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Optional names given to the hwlock specifiers in the "hwlocks" property.
|
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
|
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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