bflb,sf-flash

Overview

Name:

bflb,sf-flash

Vendor:

Bouffalo Lab (Nanjing) Co., Ltd.

Used in:

List of boards using this compatible

Description

Bouffalolab Serial Flash controller Flash

Bouffalolab Serial Flash controller Flash or device compatible with JESD216

Examples

// mx25l51245g in DIO mode.
mx25l51245g: flash@0 {
  compatible = "bflb,sf-flash", "soc-nv-flash";
  reg = <0 0x1000000>;
  write-block-size = <1>;
  erase-block-size = <DT_SIZE_K(4)>;

  spi-bus-mode = <3>;
  sf-pad = <3>;
  jedec-id = [c2 20 1a];
  use-sfdp;

  initialization-sequence = <0x06 0x0 0x0 0x1 0x0002 0x2>;
  partitions {
    #address-cells = <1>;
    #size-cells = <1>;

    storage_partition2: partition2@0 {
      compatible = "zephyr,mapped-partition";
      label = "storage_2";
      reg = <0x0 0x1000000>;
    };
  };
};

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
use-sfdp	boolean	Fetch commands from flash using SFDP instead of using defaults (Recommended). In the case of setting both 'override-bank1' and this, bank1 will use the sdfp command matching the spi-bus-mode selected, or override with dts command if it is set.
sf-pad	int	Which pad is this device using. This is directly related to which pins are used. Pad 1 is usually the embedded flash, Pad 2 and Pad 3 are usually external. Main exception is BL70x/L where the default embedded pad is SF2. External pads require a pinctrl entry at the bank. This property is required. Legal values: 1, 2, 3
spi-bus-mode	int	The width and mode of SPI bus to use for the device. Numbers refer to the number of line used in each direction. Possible values are: - IO <0> = 1-1-1 mode - DO <1> = 1-1-2 mode - QO <2> = 1-1-4 mode - DIO <3> = 1-2-2 mode - QIO <4> = 1-4-4 mode or 4-4-4 mode (QPI), or 0-4-4 mode (Continuous Read / XIP mode) This property is required. Legal values: 0, 1, 2, 3, 4
use-qpi	boolean	Enable QPI, only 4-4-4 is supported
sf-pad-is-external	boolean	Some pads can be both external and internal (like SF2 on BL70x/L). Use external pad instead of the internal one.
read-command	int	SPI command to use for memory-mapped reading.
read-dummy-cycles	int	Dummy cycles for automatic read mode. They are expressed in bytes of the address: 8 cycles with NIO, DO, QO, 4 with DIO, 2 with QIO.
continuous-read-command	int	Enable continuous read using this command setting.
write-command	int	SPI command to use for memory-mapped writing. Device must not require explicit or page sized erase.
write-dummy-cycles	int	Dummy cycles for automatic write mode. They are expressed in bytes of the address: 8 cycles with NIO, DO, QO, 4 with DIO, 2 with QIO.
initialization-sequence	array	Triples of command, data, datalength writes to set things up at setup time. For example to clear out block protection, or setup dummy timing. up to 4 bytes of data can be sent at once. Remember the byte order is inverted (right to left). Example of setting OC bits to 11 and disabling block protections on MX25L25645G: initialization-sequence = <0x06 0x0 0x0 0x1 0xc002 0x2>; If using this on internal flash this can be VERY dangerous, devcube / eflash loader is able to recover register settings in case of needs.
enter-qpi-command	int	Command to enter QPI
exit-qpi-command	int	Command to exit QPI
jedec-id	uint8-array	JEDEC ID as manufacturer ID, memory type, memory density.
read-delay	int	Flash Read delay. The default is appropriate for standard flash speed. Default value: 1 Legal values: 0, 1, 2, 3, 4
clock-invert	boolean	Invert Clock Signal.
rx-clock-invert	boolean	Invert RX Clock Signal.
quirk-bytes-write	uint8-array	Up to 4 bytes appended after the address for the auto-write command.
quirk-bytes-read	uint8-array	Up to 4 bytes appended after the address for the auto-read command.
tune-di	int	Fine tune pad delay for data in (0-3). Fine tuning is not usually necessary. Default value: 0
tune-do	int	Fine tune pad delay for data out (0-3). Fine tuning is not usually necessary. Default value: 0
tune-cs	int	Fine tune pad delay for CS (0-3). Fine tuning is not usually necessary. Default value: 0
tune-clk	int	Fine tune pad delay for CLK (0-3). Fine tuning is not usually necessary. Default value: 0
tune-oe	int	Fine tune pad delay for output enable (0-3). Fine tuning is not usually necessary. Default value: 0
erase-block-size	int	address alignment required by flash erase operations
write-block-size	int	address alignment required by flash write operations
requires-ulbpr	boolean	Indicates the device requires the ULBPR (0x98) command. Some flash chips such as the Microchip SST26VF series have a block protection register that initializes to write-protected. Use this property to indicate that the BPR must be unlocked before write operations can proceed.
has-dpd	boolean	Indicates the device supports the DPD (0xB9) command. Use this property to indicate the flash chip supports the Deep Power-Down mode that is entered by command 0xB9 to reduce power consumption below normal standby levels. Use of this property implies that the RDPD (0xAB) Release from Deep Power Down command is also supported. (On some chips this command functions as Read Electronic Signature; see t-enter-dpd).
dpd-wakeup-sequence	array	Specifies wakeup durations for devices without RDPD. Some devices (Macronix MX25R in particular) wake from deep power down by a timed sequence of CSn toggles rather than the RDPD command. This property specifies three durations measured in nanoseconds, in this order: (1) tDPDD (Delay Time for Release from Deep Power-Down Mode) (2) tCDRP (CSn Toggling Time before Release from Deep Power-Down Mode) (3) tRDP (Recovery Time for Release from Deep Power-Down Mode) Absence of this property indicates that the RDPD command should be used to wake the chip from Deep Power-Down mode.
t-enter-dpd	int	Duration required to complete the DPD command. This provides the duration, in nanoseconds, that CSn must be remain deasserted after issuing DPD before the chip will enter deep power down. If not provided the driver does not enforce a delay.
t-exit-dpd	int	Duration required to complete the RDPD command. This provides the duration, in nanoseconds, that CSn must be remain deasserted after issuing RDPD before the chip will exit deep power down and be ready to receive additional commands. If not provided the driver does not enforce a delay.
t-reset-recovery	int	Minimum time, in nanoseconds, the flash chip needs to recover after reset. Such delay is performed when a GPIO or software reset is done, or after power is supplied to the chip if the "supply-gpios" property is specified.
has-lock	int	Bit mask of bits of the status register that should be cleared on startup. Some devices from certain vendors power-up with block protect bits set in the status register, which prevent any erase or program operation from working. Devices that have this behavior need to clear those bits on startup. However, other devices have non-volatile bits in the status register that should not be cleared. This value, when present, identifies bits in the status register that should be cleared when the device is initialized.
mxicy,mx25r-power-mode	string	Select to configure flash to use ultra low power mode or high performance mode (L/H switch). The high performance mode has faster write and erase performance, but use more power than ultra low power mode. Only supported on Macronix MX25R Ultra Low Power series. Legal values: low-power, high-performance
use-4b-addr-opcodes	boolean	Indicates the device uses special 4-byte address opcodes. Instead of switching to 4-byte addressing mode, the device uses special opcodes for 4-byte addressing. Some devices support 4-byte address opcodes for read/write/erase operations. Use this property to indicate that the device supports 4-byte address opcodes.
use-flag-status-register	boolean	Indicates the device supports a flag status register. Some devices (Micron and possibly others) support a flag status register which indicates more details on the status of program or erase operations. In some cases, program operations will not function properly if the flag status register is not read after the operation.
use-fast-read	boolean	Indicates the device supports fast read. Most SPI NOR devices support a fast read command that allows the device to output data at a higher clock rate than the standard read command. This property indicates that the device supports the fast read command with 8 dummy cycles after the address phase of the command.
size	int	flash capacity in bits
sfdp-bfp	uint8-array	Contains the 32-bit words in little-endian byte order from the JESD216 Serial Flash Discoverable Parameters Basic Flash Parameters table. This provides flash-specific configuration information in cases were runtime retrieval of SFDP data is not desired.
sfdp-ff05	uint8-array	Contains the 32-bit words in little-endian byte order from the JESD216 SFDP xSPI Profile 1.0 table.
sfdp-ff84	uint8-array	Contains the 32-bit words in little-endian byte order from the JESD216 SFDP 4-byte Address Instruction Parameter table.
quad-enable-requirements	string	Quad Enable Requirements value from JESD216 BFP DW15. Use NONE if the device detects 1-1-4 and 1-4-4 modes by the instruction. Use S1B6 if QE is bit 6 of the first status register byte, and can be configured by reading then writing one byte with RDSR and WRSR. For other fields see the specification. Legal values: NONE, S2B1v1, S1B6, S2B7, S2B1v4, S2B1v5, S2B1v6
enter-4byte-addr	int	Enter 4-Byte Addressing value from JESD216 BFP DW16 This property is ignored if the device is configured to use SFDP data from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME). For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24 of DW16 identifying ways a device can be placed into 4-byte addressing mode. If provided as a non-zero value the driver assumes that 4-byte addressing is require to access the full address range, and automatically puts the device into 4-byte address mode when the device is initialized.
page-size	int	Number of bytes in a page from JESD216 BFP DW11 This property is only used in the CONFIG_SPI_NOR_SFDP_MINIMAL configuration. It is ignored if the device is configured to use SFDP data from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or if the SFDP parameters are read from the device at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME). The default value is 256 bytes if the value is not specified.