microchip,flash-g3

Description

Microchip NVMCTRL G3 Flash

Microchip NVMCTRL G3 Flash driver.

Supports the following hardware modules:
  - FCW_03433 (PIC32CK SG/GC, PIC32CZ CA) - Quad Double Word (32 B)
  - FCW_04971 (PIC32CM SG/GC) - Quad Word (16 B)

Examples

/*
 * Multiple flash regions in g3 devices are considered as a single block
 * of memory:
 *
 *   - 0x08000000--0x08020000, boot flash area
 *   - 0x0C000000--0x0C800000, main flash area
 *
 * The region in between these flash are considered as
 * unimplemented regions and driver would avoid accessing
 * these regions
 */

nvmctrl: flash-controller@44002000 {
  compatible = "microchip,nvmctrl-g3";
  reg = <0x44002000 0x200000>;
  /* ... */

  flash0: flash@8000000 {
    reg = <0x08000000
          (DT_SIZE_K(128) + DT_SIZE_K(65408) + DT_SIZE_M(8))>;
    compatible = "microchip,flash-g3", "soc-nv-flash";
    write-block-size = <8>;
    write-block-size-quad-dw = <32>;
    write-block-size-row = <1024>;
    erase-block-size = <4096>;
    unimplemented-region = <0x08020000 0x0bffffff>;
  };
};

Properties

Properties not inherited from the base binding file.

Name

Type

Details

write-block-size-quad-dw

int

Size in bytes of a quad write operation.
32 bytes (Quad Double Word) on FCW_03433 (PIC32CK SG/GC, PIC32CZ CA),
16 bytes (Quad Word) on FCW_04971 (PIC32CM SG/GC).

This property is required.

write-block-size-row

int

address alignment required by row flash write operations

unimplemented-region

array

array of unimplemented regions in the given flash area

erase-block-size

int

address alignment required by flash erase operations

write-block-size

int

address alignment required by flash write operations