microchip,xec-eeprom

Description

Microchip on-chip EEPROM

Properties

Properties not inherited from the base binding file.

Name

Type

Details

pcr-scr

int

EEPROM PCR register index and bit position

This property is required.

size

int

Total EEPROM size in bytes

read-only

boolean

Disable writes to the EEPROM

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.

girqs

array

Many DEC/MEC periperals interrupt signals are direct capable. The signals are
connected to bits in a GIRQ. Each GIRQ is composed of 5 32-bit registers:
status(latched or r/w1-c), set-enable, clr-enable, and result (read-only).
The read-only result register bits are the bitwise AND of status and enable.
Direct mode routes the individual result register bits to NVIC inputs. If
direct mode is disable by setting direct mode bit to 0 in the EC subsystem
interrupt control register then the result register outputs are OR'd together
and the OR'd result is connected to an NVIC input based on GIRQ number.
To enable an interrupt a driver must know:
a. NVIC input number and priority from the interrupts property
b. GIRQ number and bit position from the girqs property
The number of entries in interrupts and girqs should be the same in a DT node.

This property is required.