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nordic,qspi-nor (on qspi bus)

Vendor: Nordic Semiconductor

Description

QSPI NOR flash supporting the JEDEC CFI interface.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

jedec-id

uint8-array

JEDEC ID as manufacturer ID, memory type, memory density

This property is required.

size

int

The size in bits. Set this or size-in-bytes, but not both.

size-in-bytes

int

The size in bytes. Set this or size, but not both.

quad-enable-requirements

string

Quad Enable Requirements value from JESD216 BFP DW15.

Use NONE if the device detects 1-1-4 and 1-4-4 modes by the
instruction.  Use S1B6 if QE is bit 6 of the first status register
byte, and can be configured by reading then writing one byte with
RDSR and WRSR.  For other fields see the specification.

Default value: S1B6

Legal values: 'NONE', 'S2B1v1', 'S1B6', 'S2B7', 'S2B1v4', 'S2B1v5', 'S2B1v6'

readoc

string

Specify the number of data lines and opcode used for reading.
If not provided fastread will be selected.

Legal values: 'fastread', 'read2o', 'read2io', 'read4o', 'read4io'

writeoc

string

Specify the number of data lines and opcode used for writing.
If not provided pp will be selected.

Legal values: 'pp', 'pp2o', 'pp4o', 'pp4io'

address-size-32

boolean

Set to indicate that 32-bit addressing is to be used.
If not specified 24-bit addressing will be used.

ppsize-512

boolean

Set to indicate that the write opcode operates on 512-byte pages.
If not specified the write opcode operates on 256-byte pages.

sck-delay

int

Number of clock cycles CSn must be asserted before it can go low
again, specified in nanoseconds.

rx-delay

int

Number of clock cycles from the rising edge of the SPI clock
until the input serial data is sampled.

cpha

boolean

Set to indicate phase starts with asserted half-phase (CPHA=1).
For this driver using this property requires also using cpol.

cpol

boolean

Set to indicate clock leading edge is falling (CPOL=1).
For this driver using this property requires also using cpha.

sck-frequency

int

Maximum clock speed supported by the device, in Hz.

This property is required.

requires-ulbpr

boolean

Indicates the device requires the ULBPR (0x98) command.

Some flash chips such as the Microchip SST26VF series have a block
protection register that initializes to write-protected.  Use this
property to indicate that the BPR must be unlocked before write
operations can proceed.

has-dpd

boolean

Indicates the device supports the DPD (0xB9) command.

Use this property to indicate the flash chip supports the Deep
Power-Down mode that is entered by command 0xB9 to reduce power
consumption below normal standby levels.  Use of this property
implies that the RDPD (0xAB) Release from Deep Power Down command
is also supported.  (On some chips this command functions as Read
Electronic Signature; see t-enter-dpd).

dpd-wakeup-sequence

array

Specifies wakeup durations for devices without RDPD.

Some devices (Macronix MX25R in particular) wake from deep power
down by a timed sequence of CSn toggles rather than the RDPD
command.  This property specifies three durations measured in
nanoseconds, in this order:
(1) tDPDD (Delay Time for Release from Deep Power-Down Mode)
(2) tCDRP (CSn Toggling Time before Release from Deep Power-Down Mode)
(3) tRDP (Recovery Time for Release from Deep Power-Down Mode)

Absence of this property indicates that the RDPD command should be
used to wake the chip from Deep Power-Down mode.

t-enter-dpd

int

Duration required to complete the DPD command.

This provides the duration, in nanoseconds, that CSn must be
remain deasserted after issuing DPD before the chip will enter
deep power down.

If not provided the driver does not enforce a delay.

t-exit-dpd

int

Duration required to complete the RDPD command.

This provides the duration, in nanoseconds, that CSn must be
remain deasserted after issuing RDPD before the chip will exit
deep power down and be ready to receive additional commands.

If not provided the driver does not enforce a delay.

has-lock

int

Bit mask of bits of the status register that should be cleared on
startup.

Some devices from certain vendors power-up with block protect bits
set in the status register, which prevent any erase or program
operation from working.  Devices that have this behavior need to
clear those bits on startup.  However, other devices have
non-volatile bits in the status register that should not be
cleared.

This value, when present, identifies bits in the status register
that should be cleared when the device is initialized.

sfdp-bfp

uint8-array

Contains the 32-bit words in little-endian byte order from the
JESD216 Serial Flash Discoverable Parameters Basic Flash
Parameters table.  This provides flash-specific configuration
information in cases were runtime retrieval of SFDP data
is not desired.

enter-4byte-addr

int

Enter 4-Byte Addressing value from JESD216 BFP DW16

This property is ignored if the device is configured to use SFDP data
from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read
SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).

For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24
of DW16 identifying ways a device can be placed into 4-byte addressing
mode.  If provided as a non-zero value the driver assumes that 4-byte
addressing is require to access the full address range, and
automatically puts the device into 4-byte address mode when the device
is initialized.