adi,max32-pinctrl
Vendor: Analog Devices, Inc.
Description
MAX32 Pin controller Node
Based on pincfg-node.yaml binding.
Note: `bias-disable` are default pin configurations.
Properties
Top level properties
These property descriptions apply to “adi,max32-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “adi,max32-pinctrl” compatible.
Name |
Type |
Details |
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register space
This property is required. See Important properties for more information. |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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No description provided for this label
See Important properties for more information. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Power domain specifiers
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Provided names of power domain specifiers
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Number of cells in power-domains property
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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Child node properties
Name |
Type |
Details |
|---|---|---|
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Integer array, represents gpio pin number and mux setting.
These defines are calculated as: (pin<<8 | port<<4 | function<<0)
With:
- port: The gpio port index (0, 1, ...)
- pin: The pin offset within the port (0, 1, 2, ...)
- function: The function number, can be:
* 0 : GPIO
* 1 : Alternate Function 1
* 2 : Alternate Function 2
* 3 : Alternate Function 3
* 4 : Alternate Function 4
In case selected pin function is GPIO, pin is statically configured as
a plain input/output GPIO. Default configuration is input. Output value
can be configured by adding 'ouptut-low' or 'output-high' properties
to the pin configuration.
To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
-include/zephyr/dt-bindings/pinctrl/max32-pinctrl.h
Some examples of macro usage:
P0.9 set as alernate function 1
{
pinmux = <MAX32_PINMUX(0, 9, AF1)>;
};
P0.9 set as alernate function 2
{
pinmux = <MAX32_PINMUX(0, 9, AF2)>;
};
P0.9 set as GPIO output high
{
pinmux = <MAX32_PINMUX(0, 9, GPIO)>;
output-high;
};
This property is required. |
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GPIO Supply Voltage Select, Selects the voltage rail used for the pin.
0 or MAX32_VSEL_VDDIO
1 or MAX32_VSEL_VDDIOH
Legal values: |
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There are 4 drive strength mode.
Mode 0: 1mA
Mode 1: 2mA
Mode 2: 4mA
Mode 3: 8mA
Default GPIO output drive strength is mode 0 for MAX32 MCUs.
For more information please take a look device user guide, datasheet.
Legal values: |
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disable any pin bias
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enable pull-up resistor
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enable pull-down resistor
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enable input on pin (e.g. enable an input buffer, no effect on output)
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enable output on a pin without actively driving it (e.g. enable an output
buffer)
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set the pin to output mode with low level
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set the pin to output mode with high level
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