ambiq,apollo3-pinctrl
Vendor: Ambiq Micro, Inc.
Description
The Ambiq Apollo3 pin controller is a node responsible for controlling
pin function selection and pin properties, such as routing a UART0 TX
to pin 60 and enabling the pullup resistor on that pin.
The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this:
&pinctrl {
/* your modifications go here */
};
All device pin configurations should be placed in child nodes of the
'pinctrl' node, as shown in this example:
/* You can put this in places like a board-pinctrl.dtsi file in
* your board directory, or a devicetree overlay in your application.
*/
/* include pre-defined combinations for the SoC variant used by the board */
#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0TX_P60>;
};
group2 {
pinmux = <UART0RX_P47>;
input-enable;
};
};
};
The 'uart0_default' child node encodes the pin configurations for a
particular state of a device; in this case, the default (that is, active)
state.
As shown, pin configurations are organized in groups within each child node.
Each group can specify a list of pin function selections in the 'pinmux'
property.
A group can also specify shared pin properties common to all the specified
pins, such as the 'input-enable' property in group 2.
Properties
Top level properties
These property descriptions apply to “ambiq,apollo3-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “ambiq,apollo3-pinctrl” compatible.
Name |
Type |
Details |
|---|---|---|
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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register space
See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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No description provided for this label
See Important properties for more information. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Power domain specifiers
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Provided names of power domain specifiers
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Number of cells in power-domains property
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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Grandchild node properties
Name |
Type |
Details |
|---|---|---|
|
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An array of pins sharing the same group properties. Each
element of the array is an integer constructed from the
pin number and the alternative function of the pin.
This property is required. |
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The drive strength of a pin, relative to full-driver strength.
The default value is 0.1, which is the reset value of resigers
PADREGx.PADnSTRNG and ALTPADCFGx.PADn_DS1.
Default value: Legal values: |
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The 1.5K-24K pullup values are valid for select I2C enabled pads.
For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49.
The default value is 1500 ohms, which is the reset value of
register PADREGx.PADxRSEL.
Default value: Legal values: |
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IOM nCE module select, selects the SPI channel (CE) number (0-3).
The default value is 0, which is the reset value of
register CFGx.GPIOnOUTCFG. If the pin is not a CE, this
descriptor will be ignored.
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Indicates the module which uses specific CE pin, 1 if CE is IOM, 0 if MSPI.
User should check g_ui8NCEtable in am_hal_gpio.c for the mapping
information and config the pins accordingly, we give a default value
0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in
ambiq hal. If the pin is not a CE, this descriptor will be ignored.
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Indicates the instance which uses specific CE pin.
IOM number (0-5) or MSPI (0-2).
User should check g_ui8NCEtable in am_hal_gpio.c for the mapping
information and config the pins accordingly, we give a default value
0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in
ambiq hal. If the pin is not a CE, this descriptor will be ignored.
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high impedance mode ("third-state", "floating")
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enable pull-up resistor
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enable pull-down resistor
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drive actively high and low
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drive with open drain (hardware AND)
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enable input on pin (e.g. enable an input buffer, no effect on output)
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