elan,em32-pinctrl
Description
EM32 Pin controller (EM32F967).
Based on pincfg-node.yaml binding.
Note: `bias-disable` and `drive-push-pull` are the default pin
configurations. They are applied when no `bias-*` or
`drive-*` property is set in the child node.
Properties
Top level properties
These property descriptions apply to “elan,em32-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “elan,em32-pinctrl” compatible.
Name |
Type |
Details |
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Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
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This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
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Information used to define a mapping (or translation) between the address
space of a bus (the "child address space") and the address space of the
bus node's parent (the "parent address space").
The "ranges" property is typically empty, or a sequence of triplets
(child bus address, parent bus address, length).
If the "ranges" property is empty, it specifies that the parent and child
address spaces are identical and no address translation is required.
If the "ranges" property is not present in a bus node, it is assumed that
no mapping exists between children of the node and the parent address space.
For details, see "2.3.8 ranges" in Devicetree Specification v0.4.
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
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Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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Indicates that the device is capable of coherent DMA operations.
For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
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HW spinlock id relevant to the device.
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Optional names given to the hwlock specifiers in the "hwlocks" property.
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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Child node properties
Name |
Type |
Details |
|---|---|---|
|
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32-bit value encoding port, pin, mux function and (optionally)
one or two IP_SHARE register operations.
Bit layout (matches
include/zephyr/dt-bindings/pinctrl/em32f967-pinctrl.h and the
decode in drivers/pinctrl/pinctrl_em32.c):
bits [ 2:0] mux function (3 bits)
bits [ 6:3] pin number 0-15 (4 bits)
bit [ 7] port: 0 = PA, 1 = PB
bit [ 8] io1_valid (1 = first IP_SHARE op present)
bits [13:9] io1_shift (bit position 0-31 in IP_SHARE)
bits [15:14] io1_width_m1 (field width minus 1: 0 = 1 bit)
bits [19:16] io1_value (value to write at io1_shift)
bit [20] io2_valid (1 = second IP_SHARE op present)
bits [25:21] io2_shift
bits [27:26] io2_width_m1
bits [31:28] io2_value
Mux function values (3-bit field, range 0-7 — there is no
"Analog" or "GPIO=17" alias on this SoC):
* 0 : EM32F967_GPIO — plain GPIO function
* 1 : EM32F967_AF1 — alternate function 1 (SPI1, …)
* 2 : EM32F967_AF2 — alternate function 2 (UART, …)
* 3 : EM32F967_AF3 — alternate function 3 (Timer, 7816, …)
* 4 : EM32F967_AF4 — alternate function 4 (I2C, …)
* 5 : EM32F967_AF5 — alternate function 5 (I2C, WKUP, …)
* 6 : EM32F967_AF6 — alternate function 6 (reserved on PB4-PB7)
* 7 : EM32F967_AF7 — alternate function 7 (PWM, …)
When the selected mux is EM32F967_GPIO, the pin is statically
configured as a plain input/output GPIO. Default direction is
input; output value can be driven by adding `output-low` or
`output-high` to the child node.
Two helper macros are provided in
include/zephyr/dt-bindings/pinctrl/em32f967-pinctrl.h:
EM32F967_PINMUX(port, pin, mux)
Backward-compatible 3-arg form. Sets bits [7:0] only;
IP_SHARE bits [31:8] are zero. The driver falls back to
its built-in em32_ioshare_table[] lookup to configure
IP_SHARE for this pin.
EM32F967_PINMUX_IO(port, pin, mux, ioshare)
4-arg form. `ioshare` embeds one or two IP_SHARE
read-modify-write operations directly in the pinmux cell,
so the driver does not need a table lookup. Build
`ioshare` with one of:
EM32F967_IO_NONE — no IP_SHARE op
EM32F967_IO_SET_BIT(pos) — set bit `pos`
EM32F967_IO_CLR_BIT(pos) — clear bit `pos`
EM32F967_IO_SET_2BIT(pos, val) — write 2-bit field
EM32F967_IO_CLR_2BIT(pos) — clear 2-bit field
EM32F967_IO1(shift, width, val) — explicit op (slot 1)
EM32F967_IO2(shift, width, val) — explicit op (slot 2,
combine with the above using bitwise OR)
This property is required. |
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Selects WHICH internal pull-up resistor is connected when
`bias-pull-up` is also set on the same pin. It is ignored
unless `bias-pull-up` is present (multiplied by it in the SoC
Z_PINCTRL_EM32_PINCFG_INIT() macro).
1 = PU0 weak pull-up (default, == legacy `bias-pull-up;`)
2 = PU1 strong pull-up
Rationale: the standard pincfg booleans bias-disable /
bias-pull-up / bias-pull-down can only express three of the four
states of the 2-bit hardware pull field. This property exposes
the missing PU1 state without breaking existing device-tree
nodes that use the plain `bias-pull-up;` boolean.
2-bit hardware pull field (IOPUPxCTRL, 2 bits per pin):
0b00 floating <- bias-disable (or no bias property)
0b01 PU0 <- bias-pull-up [+ bias-pull-up-value = <1>]
0b10 PU1 <- bias-pull-up + bias-pull-up-value = <2>
0b11 PD <- bias-pull-down
Base Address 0x4003_0000 Offset 0x214 for GPIO PORT A (PA)
Base Address 0x4003_0000 Offset 0x218 for GPIO PORT B (PB)
GPIO Port A: PA0~6(Bit 13~0) PU0/PU1/PD:[1:0]
00: Floating
01: PU0 (Pull Up 5V→66K, 3.3V→101K, 1.8V→238K)
10: PU1 (Pull Up 5V→4.7K, 3.3V→6.41K, 1.8V→12.7K)
11: PD (Pull Down 5V→15K, 3.3V→21.8K, 1.8V→49.6K) (Default)
GPIO Port A: PA11~15(Bit 31~22) PU0/PU1/PD:[1:0]
00: Floating
01: PU0 (Pull Up 3.3V→66K, 1.8V→140K)
10: PU1 (Pull Up 3.3V→4.7K, 1.8V→8.53K)
11: PD (Pull Down 3.3V→15K, 1.8V→25.2K) (Default)
GPIO Port B(PB)(Bit 31~0) PU0/PU1/PD:[1:0]
00: Floating
01: PU0 (Pull Up 3.3V→66K, 1.8V→140K)
10: PU1 (Pull Up 3.3V→4.7K, 1.8V→8.53K)
11: PD (Pull Down 3.3V→15K, 1.8V→25.2K) (Default)
Default value: Legal values: |
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Pin output drive strength (1-bit hardware field). Use a numeric
value, e.g. `drive-strength = <1>;`.
Base Address 0x4003_0000 Offset 0x21C (PA high-drive control)
Base Address 0x4003_0000 Offset 0x220 (PB high-drive control)
0 - low drive strength when pin is configured as output (default)
4Mhz: 470uA(32mA)
1 - high drive strength when pin is configured as output
4Mhz: 490uA(65mA),
48Mhz: 5.8mA(68mA)
Default value: Legal values: |
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disable any pin bias
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enable pull-up resistor
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enable pull-down resistor
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drive actively high and low
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drive with open drain (hardware AND)
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set the pin to output mode with low level
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set the pin to output mode with high level
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