nuvoton,npcm-pinfunc

Description

Nuvoton NPCM pin function table.

Each pin's function is chosen by a selection table of SCFG DEVALTx bits. For example,
DEVALT7[6], DEVALTB[6], and DEVALT6D[7] select the function of GPIO17: 1xx is CLKOUT,
01x is RIA, 001 is I2C6B_SDA, and 000 is GPIO17.

Each child is one row of such a table, plus the function's pull and low-voltage controls
when it has them. The SoC devicetree provides the table in npcm<n>-pinfunc.dtsi. Example,
two of the GPIO17 rows:

  &pinfunc {
    pin_gpio17_gpio: pin-gpio17-gpio {
      nuvoton,alts = <NPCM_SCFG_DEVALT6D 7 0>,
                     <NPCM_SCFG_DEVALTB 6 0>,
                     <NPCM_SCFG_DEVALT7 6 0>;
    };
    pin_gpio17_sda6b: pin-gpio17-sda6b {
      nuvoton,alts = <NPCM_SCFG_DEVALT6D 7 1>,
                     <NPCM_SCFG_DEVALTB 6 0>,
                     <NPCM_SCFG_DEVALT7 6 0>;
      nuvoton,pull-up-reg = <NPCM_SCFG_DEVPD1 4>;
      nuvoton,low-voltage-reg = <NPCM_SCFG_LV_CTL3 7>;
    };
  };

Properties

Top level properties

These property descriptions apply to “nuvoton,npcm-pinfunc” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Child node properties

Name

Type

Details

nuvoton,alts

array

<register bit value> triplets for every selector bit in the pin's table row,
including the zeros, so that writing them selects exactly this function. Registers
are SCFG offsets (NPCM_SCFG_*). Absent on functions selected by a strap.

nuvoton,pull-up-reg

array

<register bit> of the function's SCFG pull-up enable.

nuvoton,pull-down-reg

array

<register bit> of the function's SCFG pull-down enable.

nuvoton,low-voltage-reg

array

<register bit> of the function's SCFG 1.8 V select.