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nuvoton,npcx-pinctrl

Vendor: Nuvoton Technology Corporation

Description

The Nuvoton pin controller is a singleton node responsible for controlling
pin function selection and pin properties. For example, you can use these
nodes to select peripheral pin functions.

Here is a list of supported standard pin properties:
  - bias-pull-down: Enable pull-down resistor.
  - bias-pull-up: Enable pull-up resistor.
  - drive-open-drain: Output driver is open-drain.

Custom pin properties for npcx series are available also:
  - pinmux-locked: Lock pinmux configuration for peripheral device
  - pinmux-gpio: Inverse pinmux back to gpio

An example for NPCX7 family, include the chip level pinctrl DTSI file in the
board level DTS:

  #include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>

We want to use the I2C0_0 port of the NPCX7M6FB controller and enable the
internal 3.3V pull-up if its i2c frequency won't exceed 400kHz.

To change a pin's pinctrl default properties, add a reference to the
pin in the board's DTS file and set the properties as below:

  &i2c0_0_sda_scl_gpb4_b5 {
    bias-pull-up; /* Enable internal pull-up for i2c0_0 */
    pinmux-locked; /* Lock pinmuxing */
  };

  &i2c0_0 {
    pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
    pinctrl-names = "default";
  }

Properties

Top level properties

These property descriptions apply to “nuvoton,npcx-pinctrl” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Child node properties

Name

Type

Details

pinmux

phandle

Configurations of pinmux selection

periph-pupd

array

A map to PUPD_ENn register/bit that enable pull-up/down of NPCX peripheral devices.
Please don't overwrite this property in the board-level DT driver.

pinmux-locked

boolean

Lock pinmux selection

pinmux-gpio

boolean

Inverse pinmux selection to GPIO

bias-pull-up

boolean

enable pull-up resistor

bias-pull-down

boolean

enable pull-down resistor

drive-open-drain

boolean

drive with open drain (hardware AND)