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nxp,mci-io-mux

Vendor: NXP Semiconductors

Description

MCI IO MUX pin control node. This node defines pin configurations in pin
groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
group within the pin configuration defines a peripheral's pin configuration.
Each numbered subgroup represents pins with shared configuration for that
peripheral. The 'pinmux' property of each group selects the pins to be
configured with these properties. For example, here is a configuration
for FLEXCOMM0 pins:

pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
  group0 {
    pinmux = <IO_MUX_FC0_USART_DATA_IO2>,
            <IO_MUX_FC0_USART_DATA_IO3>;
    slew-rate = "normal";
  };
};

If only the required properties are supplied, the pin will be configured
as normal drive strength and no pull. This corresponds to the following
pin settings:
PAD_PU_PD_ENx = (0x0 << pin_index)
SR_CONFIGx = (0x2 << pin_index)

Note

Note the inherited pinctrl properties defined below have the following effects:
bias-pull-up: PAD_PU_PD_ENx= (0x1 << pin_index)
bias-pull-down: PAD_PU_PD_ENx= (0x10 << pin_index)

Properties

Top level properties

These property descriptions apply to “nxp,mci-io-mux” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Grandchild node properties

Name

Type

Details

pinmux

array

Pin mux selection for this group. See the SOC level pinctrl header
file in NXP's HAL for a defined list of these options.

This property is required.

slew-rate

string

Pin output slew rate. Sets the GPIOxx_SR field in the SR_CONFIGx
register.
0 - slow slew rate
1 - normal slew rate
2 - fast slew rate
3 - fastest slew rate (ultra)

This property is required.

Legal values: 'slow', 'normal', 'fast', 'ultra'

bias-pull-up

boolean

enable pull-up resistor

bias-pull-down

boolean

enable pull-down resistor