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nxp,mcux-rt11xx-pinctrl

Vendor: NXP Semiconductors

Description

The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
nodes can be autogenerated using the MCUXpresso config tools combined with
the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
fields in a group select the pins to be configured, and the remaining
devicetree properties set configuration values for those pins
for example, here is an group configuring LPUART1 pins:

group0 {
    pinmux = <&iomuxc_gpio_ad_25_lpuart1_rxd>,
        <&iomuxc_gpio_ad_24_lpuart1_txd>;
    drive-strength = "high";
    slew-rate = "slow";
};

This will select GPIO_AD_25 as LPUART1 RX, and GPIO_AD_24 as LPUART1 TX.
Both pins will be configured with a weak latch, high drive strength,
and slow slew rates.
Note that the soc level iomuxc dts file can be examined to find the possible
pinmux options. Here are the affects of each property on the
IOMUXC SW_PAD_CTL register:
drive-open-drain: ODE/ODE_LPSR=1
input-enable: SION=1 (in SW_MUX_CTL_PAD register)
bias-pull-down: PUE=1, PUS=0
bias-pull-up: PUE=1, PUS=1
bias-disable: PULL=11 (in supported registers)
slew-rate: SRE=<enum_idx>
drive-strength: DSE=<enum_idx>

If only required properties are supplied, the pin will have the following
configuration:
ODE=0
SION=0
PUE=0
PUS=0
SRE=0
DSE=0

For registers with PDVR and PULL fields, these are the defaults:
PULL=11
PDRV=0

Properties

Top level properties

These property descriptions apply to “nxp,mcux-rt11xx-pinctrl” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Grandchild node properties

Name

Type

Details

pinmux

phandles

Pin mux selections for this group. See the soc level iomuxc DTSI file
for a defined list of these options.

This property is required.

drive-strength

string

Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
0 (normal) - sets pin to normal drive strength
1 (high) - sets pin to high drive strength

Legal values: 'normal', 'high'

slew-rate

string

Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
0 (fast) — Fast Slew Rate
1 (slow) — Slow Slew Rate

Legal values: 'fast', 'slow'

bias-disable

boolean

disable any pin bias

bias-pull-up

boolean

enable pull-up resistor

bias-pull-down

boolean

enable pull-down resistor

drive-open-drain

boolean

drive with open drain (hardware AND)

input-enable

boolean

enable input on pin (no effect on output, such as enabling an input
buffer)