nxp,mcux-rt266x-pinctrl
Description
The node has the 'pinctrl' node label set in an MCUX RT266x SoC's devicetree.
Unlike the RT10xx/RT11xx/RT118x parts (which expose separate SW_MUX_CTL and
SW_PAD_CTL registers), every RT266x pad is controlled by a single combined
IOMUXC PIO register. This binding therefore describes the RT266x PIO pad
fields directly, and is shared by every part in the RT266x series (RT2661/
RT2662/RT2663 and future dies built on the same IOMUXC).
The mux, mode, input, daisy, and cfg fields in a group select the pins to be
configured, and the remaining devicetree properties set configuration values
for those pins. For example, here is a group configuring LPUART0 pins:
group0 {
pinmux = <&main__iomuxc_pio3_30_hsp_lpuart0_txd>,
<&main__iomuxc_pio3_31_hsp_lpuart0_rxd>;
drive-strength = "50-ohm";
slew-rate = "fast";
};
These are the effects of each property on the IOMUXC PIO register:
drive-open-drain: ODENA=1 (PIO0..PIO4 only; PIO5/6/7 have no ODENA)
input-enable: IBENA=1 (input buffer / receiver enable)
bias-pull-down: PULLENA=0b01
bias-pull-up: PULLENA=0b10
bias-disable: PULLENA=0b00
slew-rate: SLEWRATE=<enum index>
drive-strength: DRIVE=<enum index>
If only the required properties are supplied, the pad will have PULLENA=0b00
(pull disabled), IBENA=0, ODENA=0, SLEWRATE=0b00 (low) and DRIVE=0b00
(100 ohm).
Properties
Top level properties
These property descriptions apply to “nxp,mcux-rt266x-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,mcux-rt266x-pinctrl” compatible.
Name |
Type |
Details |
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
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This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
See Important properties for more information. |
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
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Information used to define a mapping (or translation) between the address
space of a bus (the "child address space") and the address space of the
bus node's parent (the "parent address space").
The "ranges" property is typically empty, or a sequence of triplets
(child bus address, parent bus address, length).
If the "ranges" property is empty, it specifies that the parent and child
address spaces are identical and no address translation is required.
If the "ranges" property is not present in a bus node, it is assumed that
no mapping exists between children of the node and the parent address space.
For details, see "2.3.8 ranges" in Devicetree Specification v0.4.
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
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Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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Indicates that the device is capable of coherent DMA operations.
For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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The dma-ranges provides a means of defining a mapping or translation between the
physical address space of the bus and the physical address space of the parent of the bus.
For details, see "2.3.9 dma-ranges" in Devicetree Specification v0.4.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
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HW spinlock id relevant to the device.
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Optional names given to the hwlock specifiers in the "hwlocks" property.
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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Grandchild node properties
Name |
Type |
Details |
|---|---|---|
|
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Pin mux selections for this group. See the soc level iomuxc DTSI file
for a defined list of these options.
This property is required. |
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Output driver impedance. Sets the DRIVE field in the IOMUXC PIO
register. The listed values map to the register encoding in order:
100 ohm (0b00, default), 66 ohm (0b01), 50 ohm (0b10), 33 ohm (0b11) --
the encoding the SDK header documents for IOMUXC_PIO_DRIVE. Lower
impedance yields a stronger drive.
A string enum rather than an integer, matching slew-rate here and every
other NXP pinctrl binding: the value is consumed by DT_ENUM_IDX, which
reads its position in this list and never the number itself, so an
integer would advertise arithmetic that does not happen.
Deliberately no default. Omitting the property leaves DRIVE at its reset
value, which is 100 ohm, so a default would only be redundant -- and it
would defeat the build-time check that rejects this property on the
PIO0..PIO4 pads, which have no DRIVE field: a binding default is
materialized for every group, making "the user asked for this"
indistinguishable from "the binding filled it in".
Only the PIO5, PIO6 and PIO7 pads have a DRIVE field. On the PIO0
(VBAT), PIO1 (WAKE) and PIO2/PIO3/PIO4 (MAIN) pads this property
has no effect and is not written.
Legal values: |
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Pad slew rate. Sets the SLEWRATE field in the IOMUXC PIO register.
The listed values map to the register encoding in order:
low (0b00, default), medium (0b01), fast (0b10), high (0b11).
SLEWRATE is 2 bits wide only on the PIO5, PIO6 and PIO7 pads. On
the PIO0, PIO1 and PIO2/PIO3/PIO4 pads it is a single bit, so any
value above "low" selects that pad's one fast setting.
Default value: Legal values: |
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disable any pin bias
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enable pull-up resistor
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enable pull-down resistor
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drive with open drain (hardware AND)
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enable input on pin (e.g. enable an input buffer, no effect on output)
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