nxp,port-pinctrl

Description

NXP PORT pinctrl node. This node will define pin configurations in pin
groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
group within the pin configuration defines the pin configuration for a
peripheral, and each numbered subgroup in the pin group defines all the pins
for that peripheral with the same configuration properties. The 'pins'
property in a group selects the pins to be configured, and the remaining
properties set configuration values for those pins. Here is an example
group for UART0 pins:

uart0_default: uart0_default {
  group0 {
    pins = <UART0_RX_PTB16
      UART0_TX_PTB17>;
    drive-strength = "low";
    slew-rate = "fast";
    };
};

If only the required properties are supplied, the pin configuration register
will be assigned the following values:
PCR_PS=0,
PCR_PE=0,
PCR_ODE=0,
PCR_SRE=<slew-rate selection>,
PCR_DSE=<drive-strength selection>,
PCR_PFE=0

Properties

Top level properties

These property descriptions apply to “nxp,port-pinctrl” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,port-pinctrl” compatible.

Name	Type	Details
`status`	`string`	indicates the operational status of a device Legal values: `'ok'`, `'okay'`, `'disabled'`, `'reserved'`, `'fail'`, `'fail-sss'` See Important properties for more information.
`compatible`	`string-array`	compatible strings This property is required. See Important properties for more information.
`reg`	`array`	register space See Important properties for more information.
`reg-names`	`string-array`	name of each register space
`interrupts`	`array`	interrupts for device See Important properties for more information.
`interrupts-extended`	`compound`	extended interrupt specifier for device
`interrupt-names`	`string-array`	name of each interrupt
`interrupt-parent`	`phandle`	phandle to interrupt controller node
`label`	`string`	No description provided for this label See Important properties for more information.
`clocks`	`phandle-array`	Clock gate information
`clock-names`	`string-array`	name of each clock
`#address-cells`	`int`	number of address cells in reg property
`#size-cells`	`int`	number of size cells in reg property
`dmas`	`phandle-array`	DMA channels specifiers
`dma-names`	`string-array`	Provided names of DMA channel specifiers
`io-channels`	`phandle-array`	IO channels specifiers
`io-channel-names`	`string-array`	Provided names of IO channel specifiers
`mboxes`	`phandle-array`	mailbox / IPM channels specifiers
`mbox-names`	`string-array`	Provided names of mailbox / IPM channel specifiers
`power-domains`	`phandle-array`	Power domain specifiers
`power-domain-names`	`string-array`	Provided names of power domain specifiers
`#power-domain-cells`	`int`	Number of cells in power-domains property
`zephyr,deferred-init`	`boolean`	Do not initialize device automatically on boot. Device should be manually initialized using device_init().
`wakeup-source`	`boolean`	Property to identify that a device can be used as wake up source. When this property is provided a specific flag is set into the device that tells the system that the device is capable of wake up the system. Wake up capable devices are disabled (interruptions will not wake up the system) by default but they can be enabled at runtime if necessary.
`zephyr,pm-device-runtime-auto`	`boolean`	Automatically configure the device for runtime power management after the init function runs.
`zephyr,disabling-power-states`	`phandles`	List of power states that will disable this device power.

Grandchild node properties

Name	Type	Details
`pinmux`	`array`	Pin mux selections for this group. See the soc level pinctrl DTSI file in NXP's HAL for a defined list of these options This property is required.
`drive-strength`	`string`	Pin output drive strength. Sets the DSE field in the PORTx_PCRn register. 0 DSE_0- low drive strength when pin is configured as output 1 DSE_1- high drive strength when pin is configured as output This property is required. Legal values: `'low'`, `'high'`
`slew-rate`	`string`	Pin output slew rate. Sets the SRE field in the PORTx_PCRn register. 0 SRE_0_fast- fast slew rate when pin is configured as output 1 SRE_1_slow- slow slew rate when pin is configured as output Legal values: `'fast'`, `'slow'`
`nxp,passive-filter`	`boolean`	Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.
`bias-pull-up`	`boolean`	enable pull-up resistor
`bias-pull-down`	`boolean`	enable pull-down resistor
`drive-open-drain`	`boolean`	drive with open drain (hardware AND)
`input-enable`	`boolean`	enable input on pin (e.g. enable an input buffer, no effect on output)