st,stm32wba-pwr

Description

STM32WBA power controller

Power controller of STM32WBA series

Controls the memory retained in s2ram power state.

Examples

/*
 * Not used RAM retained (and so powered) is simply a
 * pointless waste of energy.
 * `/chosen/zephyr,sram` (Zephyr system memory) is mapped on
 * sram0 memory controller.
 * According the required ram, sram0 memory controller will use
 * SRAM1 (up to 448KB) and SRAM2 (up to 64KB) physical banks.
 *
 * Let's imagine a build report shows an application needs
 * 120 KB of RAM and Standby low-power feature is required.
 * In this case only the first 2 pages of SRAM1 will be retained.
 * And SRAM2 is not retained by default.
 * The overlay file can be modified like this:
 */
sram0: memory@20000000 {
        reg = <0x20000000 DT_SIZE_K(120)>;
};

/*
 * If for any specific reason application needs to retain SRAM2:
 */
&pwr {
        power-supply = "smps";
        retain-sram2;
        status = "okay";
};

/*
 * If full memory is required, SRAM1 and SRAM2 will be
 * fully retained and the sram0 memory node will appear
 * like this:
 */
sram0: memory@20000000 {
        reg = <0x20000000 DT_SIZE_K(512)>;
};

Properties

Top level properties

These property descriptions apply to “st,stm32wba-pwr” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

Name

Type

Details

retain-sram2

boolean

Enables retention of SRAM2 while in Standby low-power mode.
(Standby mode is a suspend-to-RAM power state)

If this property is present, the entire SRAM2 memory region
will be retained in Standby mode (all contents preserved).

If this property is not present, the SRAM2 memory region will
will not be retained in Standby mode (all contents are lost),
except if the Zephyr RAM region `/chosen/zephyr,sram` overlaps
with SRAM2 (in this case, retention is always enabled).

power-supply

string

Power supply configuration

This property specifies the voltage regulators configuration
and indicates how the core domain voltage (Vcore) is generated.
Refer to your product's Datasheet and Reference Manual for details.

ldo: LDO supply
  The LDO is enabled and generates Vcore; the SMPS is disabled.

smps: SMPS supply
  The SMPS is enabled and generates Vcore; the LDO is disabled.

This property is required.

Legal values: ldo, smps

wkup-pins-nb

int

Max nbr of system wake-up pins.
For example wkup-pins-nb = <8>; on the stm32u5

wkup-pin-srcs

int

Number of wake-up GPIO sources to select from for each wake-up pin.
If not specified, that means there is only 1 GPIO source for each
wake-up pin.

For example, each wake-up pin on STM32U5 is associated with
4 wake-up sources, 3 of them correspond to GPIOs.

wkup-pins-pol

boolean

True if SoC has a wake-up pins polarity config register

wkup-pins-pupd

boolean

True if SoC has pull-up/down config register(s) for GPIO ports
that are associated with wake-up pins.

Child node properties

Name

Type

Details

reg

array

Wake-up pin identifier, same as "index" in node name

This property is required.

See Important properties for more information.

wkup-gpios

phandle-array

Specifies the GPIOs, if any, that are associated with the wake-up pin.

For example, for GPIO PB2 associated with wakeup source 1 on wake-up
event 1 on STM32U5 SoCs:
wkup-gpios = <&gpiob 2 STM32_PWR_WKUP_EVT_SRC_1>, <...>;