adi,ad2s1210 (on spi bus)

Vendor: Analog Devices, Inc.

Note

An implementation of a driver matching this compatible is available in drivers/sensor/adi/ad2s1210/ad2s1210.c.

Description

AD2S1210 resolution tracking resolver-to-digital converter

The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
resolver-to-digital converter, integrating an on-board programmable
sinusoidal oscillator that provides sine wave excitation for
resolvers.

The AD2S1210 allows the user to read the angular position or the
angular velocity data directly from the parallel outputs or through
the serial interface.

The mode of operation of the communication channel (parallel or serial) is
selected by the A0 and A1 input pins. In normal mode, data is latched by
toggling the SAMPLE line and can then be read directly. In configuration mode,
data is read or written using a register access scheme (address byte with
read/write flag and data byte).

  A1  A0  Result
   0   0  Normal mode - position output
   0   1  Normal mode - velocity output
   1   0  Reserved
   1   1  Configuration mode

In normal mode, the resolution of the digital output is selected using
the RES0 and RES1 input pins. In configuration mode, the resolution is
selected by setting the RES0 and RES1 bits in the control register.

RES1  RES0  Resolution (Bits)
   0     0  10
   0     1  12
   1     0  14
   1     1  16

Note on SPI connections: The CS line on the AD2S1210 should hard-wired to
logic low and the WR/FSYNC line on the AD2S1210 should be connected to the
SPI CSn output of the SPI controller.

Datasheet:
https://www.analog.com/media/en/technical-documentation/data-sheets/ad2s1210.pdf

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
sample-gpios	phandle-array	GPIO connected to the /SAMPLE pin. As the line needs to be low to trigger a sample, it should be configured as GPIO_ACTIVE_LOW. This property is required.
mode-gpios	phandle-array	GPIO lines connected to the A0 and A1 pins. These pins select the data transfer mode. This property is required.
reset-gpios	phandle-array	GPIO connected to the /RESET pin. As the line needs to be low for the reset to be active, it should be configured as GPIO_ACTIVE_LOW. This property is required.
resolution-gpios	phandle-array	GPIO lines connected to the RES0 and RES1 pins. These pins select the resolution of the digital output. If omitted, it is assumed that the RES0 and RES1 pins are hard-wired to match the assigned-resolution-bits property.
fault-gpios	phandle-array	GPIO lines connected to the LOT and DOS pins. These pins combined indicate the type of fault present, if any. As these pins a pulled low to indicate a fault condition, they should be configured as GPIO_ACTIVE_LOW.
assigned-resolution-bits	int	Resolution of the digital output required by the application. This determines the precision of the angle and/or the maximum speed that can be measured. If resolution-gpios is omitted, it is assumed that RES0 and RES1 are hard-wired to match this value. Default resolution at power up for the configuration mode is 12 bits so we are using 12 bits as default here as well. Default value: 12 Legal values: 10, 12, 14, 16
clock-frequency	int	Frequency of the resolver clock input signal in Hz. Range is 6144000 and 10240000. This property is required.
spi-max-frequency	int	Maximum clock frequency of device's SPI interface in Hz This property is required.
duplex	int	Duplex mode, full or half. By default it's always full duplex thus 0 as this is, by far, the most common mode. Use the macros not the actual enum value, here is the concordance list (see dt-bindings/spi/spi.h) 0 SPI_FULL_DUPLEX 2048 SPI_HALF_DUPLEX Legal values: 0, 2048
frame-format	int	Motorola or TI frame format. By default it's always Motorola's, thus 0 as this is, by far, the most common format. Use the macros not the actual enum value, here is the concordance list (see dt-bindings/spi/spi.h) 0 SPI_FRAME_FORMAT_MOTOROLA 32768 SPI_FRAME_FORMAT_TI Legal values: 0, 32768
spi-cpol	boolean	SPI clock polarity which indicates the clock idle state. If it is used, the clock idle state is logic high; otherwise, low.
spi-cpha	boolean	SPI clock phase that indicates on which edge data is sampled. If it is used, data is sampled on the second edge; otherwise, on the first edge.
spi-hold-cs	boolean	In some cases, it is necessary for the master to manage SPI chip select under software control, so that multiple spi transactions can be performed without releasing it. A typical use case is variable length SPI packets where the first spi transaction reads the length and the second spi transaction reads length bytes.
supply-gpios	phandle-array	GPIO specifier that controls power to the device. This property should be provided when the device has a dedicated switch that controls power to the device. The supply state is entirely the responsibility of the device driver. Contrast with vin-supply.
vin-supply	phandle	Reference to the regulator that controls power to the device. The referenced devicetree node must have a regulator compatible. This property should be provided when device power is supplied by a shared regulator. The supply state is dependent on the request status of all devices fed by the regulator. Contrast with supply-gpios. If both properties are provided then the regulator must be requested before the supply GPIOS is set to an active state, and the supply GPIOS must be set to an inactive state before releasing the regulator.
friendly-name	string	Human readable string describing the sensor. It can be used to distinguish multiple instances of the same model (e.g., lid accelerometer vs. base accelerometer in a laptop) to a host operating system. This property is defined in the Generic Sensor Property Usages of the HID Usage Tables specification (https://usb.org/sites/default/files/hut1_3_0.pdf, section 22.5).