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altr,jtag-uart

Vendor: Altera Corp.

Description

These nodes are “uart” bus nodes.

Altera JTAG UART

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

Clock frequency information for UART operation

current-speed

int

Initial baud rate setting for UART

hw-flow-control

boolean

Set to enable RTS/CTS flow control at boot time

parity

string

Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
and 2 for even parity. Default to none if not specified.

Legal values: 'none', 'odd', 'even'

stop-bits

string

Sets the number of stop bits.

Legal values: '0_5', '1', '1_5', '2'

data-bits

int

Sets the number of data bits.

Legal values: 5, 6, 7, 8, 9

write-fifo-depth

int

Buffer size of transmit fifo. This used to implement irq_tx_complete.
Must be same as Write FIFO: Buffer depth (bytes) in platform designer.

Default value: 64