infineon,xmc4xxx-uart

Vendor: Infineon Technologies

Note

An implementation of a driver matching this compatible is available in drivers/serial/uart_xmc4xxx.c.

Description

These nodes are “uart” bus nodes.

INFINEON XMC4XXX UART

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

Clock frequency information for UART operation

current-speed

int

Initial baud rate setting for UART

hw-flow-control

boolean

Set to enable RTS/CTS flow control at boot time

parity

string

Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
and 2 for even parity. Default to none if not specified.

Legal values: 'none', 'odd', 'even'

stop-bits

string

Sets the number of stop bits.

Legal values: '0_5', '1', '1_5', '2'

data-bits

int

Sets the number of data bits.

Legal values: 5, 6, 7, 8, 9

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.

This property is required.

input-src

string

Connects the UART receive line (USIC DX0 input) to a specific GPIO pin.
The USIC DX0 input is a multiplexer which connects to different GPIO pins.
Refer to the XMC4XXX reference manual for the GPIO pin/mux mappings. DX0G
is the loopback input line.

This property is required.

Legal values: 'DX0A', 'DX0B', 'DX0C', 'DX0D', 'DX0E', 'DX0F', 'DX0G'

fifo-start-offset

int

Each USIC0..2 has a fifo that is shared between two channels. For example,
usic0ch0 and usic0ch1 will share the same fifo. This parameter defines an offset
where the tx and rx fifos will start. When sharing the fifo, the user must properly
define the offset based on the configuration of the other channel. The fifo has a
capacity of 64 entries. The tx/rx fifos are created on fifo-xx-size aligned
boundaries.

This property is required.

fifo-tx-size

int

Fifo size used for buffering transmit bytes. A value of 0 implies that
the fifo is not used while transmitting. transmitting. If the UART is used in async mode
then fifo-tx-size should be set to 0.

This property is required.

Legal values: 0, 2, 4, 8, 16, 32, 64

fifo-rx-size

int

Fifo size used for buffering received bytes. A value of 0 implies that
the fifo is not used while receiving. If the UART is used in async mode
then fifo-rx-size should be set to 0.

This property is required.

Legal values: 0, 2, 4, 8, 16, 32, 64