st,stm32-lpuart

Vendor: STMicroelectronics

Description

These nodes are “uart” bus nodes.

STM32 LPUART

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
resets	phandle-array	Reset information This property is required.
single-wire	boolean	Enable the single wire half-duplex communication. Using this mode, TX and RX lines are internally connected and only TX pin is used afterwards and should be configured. RX/TX conflicts must be handled on user side.
tx-rx-swap	boolean	Swap the TX and RX pins. Used in case of a cross wired connection.
pinctrl-0	phandles	Pin configuration/s for the first state. Content is specific to the selected pin controller driver implementation. This property is required.
pinctrl-names	string-array	Names for the provided states. The number of names needs to match the number of states. This property is required.
wakeup-line	int	EXTI line number matching the device wakeup interrupt mask register. This property is required on stm32 devices where the wakeup interrupt signal could be configured masked at boot (sm32wl55 for instance), preventing the device to wakeup the core from stop mode(s). Valid range: 0 - 31
de-enable	boolean	Enable activating an external transeiver through the DE pin which must also be configured using pinctrl.
de-assert-time	int	Defines the time between the activation of the DE signal and the beginning of the start bit. It is expressed in 16th of a bit time. Valid range: 0 - 31
de-deassert-time	int	Defines the time between the activation of the DE signal and the beginning of the start bit. It is expressed in 16th of a bit time. Valid range: 0 - 31
de-invert	boolean	Invert the binary logic of the de pin. When enabled, physical logic levels are inverted and we use 1=Low, 0=High instead of 1=High, 0=Low.
fifo-enable	boolean	Enables transmit and receive FIFO using default FIFO configuration (typically threshold is set to 1/8). In TX, FIFO allows to work in burst mode, easing scheduling of loaded applications. It also allows more reliable communication with UART devices sensitive to variation of inter-frames delays. In RX, FIFO reduces overrun occurrences.
current-speed	int	Initial baud rate setting for UART
hw-flow-control	boolean	Set to enable RTS/CTS flow control at boot time
parity	string	Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd and 2 for even parity. Default to none if not specified. Legal values: 'none', 'odd', 'even'
stop-bits	string	Sets the number of stop bits. Legal values: '0_5', '1', '1_5', '2'
data-bits	int	Sets the number of data bits. Legal values: 5, 6, 7, 8, 9
pinctrl-1	phandles	Pin configuration/s for the second state. See pinctrl-0.
pinctrl-2	phandles	Pin configuration/s for the third state. See pinctrl-0.
pinctrl-3	phandles	Pin configuration/s for the fourth state. See pinctrl-0.
pinctrl-4	phandles	Pin configuration/s for the fifth state. See pinctrl-0.
reset-names	string-array	Name of each reset
tx-invert	boolean	Invert the binary logic of tx pin. When enabled, physical logic levels are inverted and we use 1=Low, 0=High instead of 1=High, 0=Low.
rx-invert	boolean	Invert the binary logic of rx pin. When enabled, physical logic levels are inverted and we use 1=Low, 0=High instead of 1=High, 0=Low.