aptina,mt9m114 (on i2c bus)

Vendor: Aptina Imaging

Note

An implementation of a driver matching this compatible is available in drivers/video/mt9m114.c.

Description

MT9M114 CMOS video sensor

Properties

Top level properties

These property descriptions apply to “aptina,mt9m114” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

Name

Type

Details

supply-gpios

phandle-array

GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

Grandchild node properties

Name

Type

Details

remote-endpoint-label

string

Label of the 'remote-endpoint' subnode that interfaces with this endpoint.
This property is used as a 'work-around' to be able to declare the remote
endpoint and should be replaced by a "remote-endpoint" phandle property when
Zephyr devicetree supports circular dependency in the future.

This property is required.

bus-type

int

Data bus type.

Legal values: 1, 2, 3, 4, 5, 6

data-shift

int

On parallel data busses, if bus-width is used to specify the number of
data lines, data-shift can be used to specify which data lines are used,
e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.

hsync-active

int

Active state of the HSYNC signal

Legal values: 0, 1

vsync-active

int

Active state of the VSYNC signal.

Legal values: 0, 1

pclk-sample

int

Sample data on falling, rising or both edges of the pixel clock signal.

Legal values: 0, 1, 2

link-frequencies

array

Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the
actual frequency of the bus, not bits per clock per lane value.

clock-lane

int

Physical clock lane index. Position of an entry determines the logical
lane number, while the value of an entry indicates physical lane, e.g. for
a MIPI CSI-2 bus we could have "clock-lane = <0>;", which places the
clock lane on hardware lane 0. This property is valid for serial busses
only (e.g. MIPI CSI-2).

data-lanes

array

An array of physical data lane indexes. Position of an entry determines
the logical lane number, while the value of an entry indicates physical
lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
assuming the clock lane is on hardware lane 0. If the hardware does not
support lane reordering, monotonically incremented values shall be used
from 0 or 1 onwards, depending on whether or not there is also a clock
lane. This property is valid for serial busses only (e.g. MIPI CSI-2).

bus-width

int

Number of data lines actively used, only valid for parallel busses.