nxp,xspi

Description

These nodes are “spi” bus nodes.

NXP XSPI controller

Properties

Top level properties

These property descriptions apply to “nxp,xspi” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

Name

Type

Details

byte-order

int

Byte ordering endianness.
0 = 64-bit BE, 1 = 32-bit LE, 2 = 32-bit BE, 3 = 64-bit LE

Default value: 3

Legal values: 0, 1, 2, 3

enable-ahb-write

boolean

Enable AHB write access.

ahb-buffer-write-flush

boolean

Enable flushing AHB buffer on write or IP access.

ahb-prefetch

boolean

Enable AHB read prefetch feature.

clock-frequency

int

Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

overrun-character

int

The overrun character (ORC) is used when all bytes from the TX buffer
are sent, but the transfer continues due to RX.

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.

Child node properties

Name

Type

Details

enable-descriptor-lock

int

Enable descriptor lock

mask-type

int

Mask type (0=AND, 1=OR)

mask

int

6-bit mask value

master-id-reference

int

Master ID reference value

secure-attribute

int

Security attribute setting

Legal values: 1, 2, 3

start-address

int

Start address of the memory region

end-address

int

End address of the memory region

tg0-master-access

int

Target group 0 access permissions

tg1-master-access

int

Target group 1 access permissions

descriptor-lock

int

Descriptor lock mode:
- Disable
- Enable till hard reset
- Enable except master ID
- Enable

Legal values: 0, 1, 2, 3

exclusive-access-lock

int

Exclusive access lock mode:
- Disable
- Enable except master ID
- Enable

Legal values: 0, 2, 3