amebag2_clock.h File Reference

Realtek Amebag2 clock Devicetree bindings. More...

Go to the source code of this file.

Macros
AON domain clocks
#define	AMEBA_ATIM_CLK   1
	ATIM clock in AON domain.
#define	AMEBA_RTC_CLK   2
	RTC clock in AON domain.
#define	AMEBA_LEDC_CLK   3
	LEDC clock in AON domain.
SYSON domain clocks
#define	AMEBA_PWM0_CLK   4
	PWM0 clock in SYSON domain.
#define	AMEBA_PWM1_CLK   5
	PWM1 clock in SYSON domain.
#define	AMEBA_PWM2_CLK   6
	PWM2 clock in SYSON domain.
#define	AMEBA_PWM3_CLK   7
	PWM3 clock in SYSON domain.
#define	AMEBA_PWM4_CLK   8
	PWM4 clock in SYSON domain.
#define	AMEBA_UART0_CLK   9
	UART0 clock in SYSON domain.
#define	AMEBA_UART1_CLK   10
	UART1 clock in SYSON domain.
#define	AMEBA_UART2_CLK   11
	UART2 clock in SYSON domain.
#define	AMEBA_UART3_CLK   12
	UART3 clock in SYSON domain.
#define	AMEBA_LOGUART_CLK   13
	LOGUART clock in SYSON domain.
#define	AMEBA_DTIM_CLK   14
	DTIM clock in SYSON domain.
#define	AMEBA_ADC_CLK   15
	ADC clock in SYSON domain.
#define	AMEBA_GPIO_CLK   16
	GPIO clock in SYSON domain.
#define	AMEBA_LTIM0_CLK   17
	LTIM0 clock in SYSON domain.
#define	AMEBA_LTIM1_CLK   18
	LTIM1 clock in SYSON domain.
#define	AMEBA_LTIM2_CLK   19
	LTIM2 clock in SYSON domain.
#define	AMEBA_LTIM3_CLK   20
	LTIM3 clock in SYSON domain.
#define	AMEBA_PTIM0_CLK   21
	PTIM0 clock in SYSON domain.
#define	AMEBA_PTIM1_CLK   22
	PTIM1 clock in SYSON domain.
SoC domain clocks
#define	AMEBA_DMAC_CLK   23
	DMAC clock in SoC domain.
#define	AMEBA_SDH_CLK   24
	SDH clock in SoC domain.
#define	AMEBA_SDD_CLK   25
	SDD clock in SoC domain.
#define	AMEBA_SPI0_CLK   26
	SPI0 clock in SoC domain.
#define	AMEBA_SPI1_CLK   27
	SPI1 clock in SoC domain.
#define	AMEBA_USB_CLK   28
	USB clock in SoC domain.
#define	AMEBA_FLASH_CLK   29
	Flash clock in SoC domain.
#define	AMEBA_PSRAM_CLK   30
	PSRAM clock in SoC domain.
#define	AMEBA_SPORT_CLK   31
	SPORT clock in SoC domain.
#define	AMEBA_AC_CLK   32
	AC clock in SoC domain.
#define	AMEBA_IRDA_CLK   33
	IRDA clock in SoC domain.
#define	AMEBA_I2C0_CLK   34
	I2C0 clock in SoC domain.
#define	AMEBA_I2C1_CLK   35
	I2C1 clock in SoC domain.
#define	AMEBA_TRNG_CLK   36
	TRNG clock in SoC domain.
#define	AMEBA_LCDC_CLK   37
	LCDC clock in SoC domain.
#define	AMEBA_A2C0_CLK   38
	A2C0 clock in SoC domain.
#define	AMEBA_A2C1_CLK   39
	A2C1 clock in SoC domain.
#define	AMEBA_GMAC_CLK   40
	GMAC clock in SoC domain.
#define	AMEBA_PPE_CLK   41
	PPE clock in SoC domain.
#define	AMEBA_MJPEG_CLK   42
	MJPEG clock in SoC domain.
Misc clocks
#define	AMEBA_BTON_CLK   43
	BTON clock.
#define	AMEBA_PKE_CLK   44
	PKE clock (misc domain).
#define	AMEBA_CLK_MAX   45 /* clk idx max */
	Maximum clock index (one past the last valid index).
Peripheral clock helper macros
#define	AMEBA_NUMERICAL_PERIPH(name, n)
	Define a clock entry for a peripheral with numerical suffix.
#define	AMEBA_SINGLE_PERIPH(name)
	Define a clock entry for a single-instance peripheral.
#define	AMEBA_SINGLE_PERIPH_NO_FEN(name)
	Define a clock entry for a single-instance peripheral without FEN bit.
#define	AMEBA_LTIM_PERIPHS
	LTIM clock peripheral mappings.
#define	AMEBA_PTIM_PERIPHS
	PTIM clock peripheral mappings.
#define	AMEBA_SPI_PERIPHS
	SPI clock peripheral mappings.
#define	AMEBA_I2C_PERIPHS
	I2C clock peripheral mappings.
#define	AMEBA_PWM_PERIPHS
	PWM clock peripheral mappings.
#define	AMEBA_UART_PERIPHS
	UART clock peripheral mappings.
#define	AMEBA_A2C_PERIPHS
	A2C clock peripheral mappings.
#define	AMEBA_LOGUART_PERIPHS   AMEBA_SINGLE_PERIPH(LOGUART) /* AMEBA_LOGUART_CLK */
	LOGUART clock peripheral mapping.
#define	AMEBA_DMAC_PERIPHS   AMEBA_SINGLE_PERIPH(DMAC) /* AMEBA_DMAC_CLK */
	DMAC clock peripheral mapping.
#define	AMEBA_SDH_PERIPHS   AMEBA_SINGLE_PERIPH(SDH) /* AMEBA_SDH_CLK */
	SDH clock peripheral mapping.
#define	AMEBA_SDD_PERIPHS   AMEBA_SINGLE_PERIPH(SDD) /* AMEBA_SDD_CLK */
	SDD clock peripheral mapping.
#define	AMEBA_USB_PERIPHS   AMEBA_SINGLE_PERIPH(USB) /* AMEBA_USB_CLK */
	USB clock peripheral mapping.
#define	AMEBA_FLASH_PERIPHS   AMEBA_SINGLE_PERIPH(FLASH) /* AMEBA_FLASH_CLK */
	Flash clock peripheral mapping.
#define	AMEBA_PSRAM_PERIPHS   AMEBA_SINGLE_PERIPH(PSRAM) /* AMEBA_PSRAM_CLK */
	PSRAM clock peripheral mapping.
#define	AMEBA_AC_PERIPHS   AMEBA_SINGLE_PERIPH(AC) /* AMEBA_AC_CLK */
	AC clock peripheral mapping.
#define	AMEBA_IRDA_PERIPHS   AMEBA_SINGLE_PERIPH(IRDA) /* AMEBA_IRDA_CLK */
	IRDA clock peripheral mapping.
#define	AMEBA_TRNG_PERIPHS   AMEBA_SINGLE_PERIPH(TRNG) /* AMEBA_TRNG_CLK */
	TRNG clock peripheral mapping.
#define	AMEBA_LCDC_PERIPHS   AMEBA_SINGLE_PERIPH(LCDC) /* AMEBA_LCDC_CLK */
	LCDC clock peripheral mapping.
#define	AMEBA_RTC_PERIPHS   AMEBA_SINGLE_PERIPH_NO_FEN(RTC) /* AMEBA_RTC_CLK */
	RTC clock peripheral mapping (no FEN bit).
#define	AMEBA_LEDC_PERIPHS   AMEBA_SINGLE_PERIPH(LEDC) /* AMEBA_LEDC_CLK */
	LEDC clock peripheral mapping.
#define	AMEBA_ADC_PERIPHS   AMEBA_SINGLE_PERIPH(ADC) /* AMEBA_ADC_CLK */
	ADC clock peripheral mapping.
#define	AMEBA_GPIO_PERIPHS   AMEBA_SINGLE_PERIPH(GPIO) /* AMEBA_GPIO_CLK */
	GPIO clock peripheral mapping.
#define	AMEBA_BTON_PERIPHS   AMEBA_SINGLE_PERIPH(BTON) /* AMEBA_BTON_CLK */
	BTON clock peripheral mapping.
#define	AMEBA_SPORT_PERIPHS   AMEBA_SINGLE_PERIPH(SPORT) /* AMEBA_SPORT_CLK */
	SPORT clock peripheral mapping.
#define	AMEBA_GMAC_PERIPHS   AMEBA_SINGLE_PERIPH(GMAC) /* AMEBA_GMAC_CLK */
	GMAC clock peripheral mapping.
#define	AMEBA_PPE_PERIPHS   AMEBA_SINGLE_PERIPH(PPE) /* AMEBA_PPE_CLK */
	PPE clock peripheral mapping.
#define	AMEBA_MJPEG_PERIPHS   AMEBA_SINGLE_PERIPH(MJPEG) /* AMEBA_MJPEG_CLK */
	MJPEG clock peripheral mapping.
#define	AMEBA_CORE_PERIPHS
	Aggregated core peripheral clock mappings.

Detailed Description

Realtek Amebag2 clock Devicetree bindings.

Macro Definition Documentation

AMEBA_A2C0_CLK

#define AMEBA_A2C0_CLK   38

A2C0 clock in SoC domain.

AMEBA_A2C1_CLK

#define AMEBA_A2C1_CLK   39

A2C1 clock in SoC domain.

AMEBA_A2C_PERIPHS

#define AMEBA_A2C_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(A2C, 0) /* AMEBA_A2C0_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(A2C, 1) /* AMEBA_A2C1_CLK */

A2C clock peripheral mappings.

AMEBA_AC_CLK

#define AMEBA_AC_CLK   32

AC clock in SoC domain.

AMEBA_AC_PERIPHS

#define AMEBA_AC_PERIPHS   AMEBA_SINGLE_PERIPH(AC) /* AMEBA_AC_CLK */

AC clock peripheral mapping.

AMEBA_ADC_CLK

#define AMEBA_ADC_CLK   15

ADC clock in SYSON domain.

AMEBA_ADC_PERIPHS

#define AMEBA_ADC_PERIPHS   AMEBA_SINGLE_PERIPH(ADC) /* AMEBA_ADC_CLK */

ADC clock peripheral mapping.

AMEBA_ATIM_CLK

#define AMEBA_ATIM_CLK   1

ATIM clock in AON domain.

AMEBA_BTON_CLK

#define AMEBA_BTON_CLK   43

BTON clock.

AMEBA_BTON_PERIPHS

#define AMEBA_BTON_PERIPHS   AMEBA_SINGLE_PERIPH(BTON) /* AMEBA_BTON_CLK */

BTON clock peripheral mapping.

AMEBA_CLK_MAX

#define AMEBA_CLK_MAX   45 /* clk idx max */

Maximum clock index (one past the last valid index).

AMEBA_CORE_PERIPHS

#define AMEBA_CORE_PERIPHS

Value:

        AMEBA_RTC_PERIPHS                                                                  \
        AMEBA_PWM_PERIPHS                                                                  \
        AMEBA_LEDC_PERIPHS                                                                 \
        AMEBA_UART_PERIPHS                                                                 \
        AMEBA_LOGUART_PERIPHS                                                              \
        AMEBA_ADC_PERIPHS                                                                  \
        AMEBA_GPIO_PERIPHS                                                                 \
        AMEBA_LTIM_PERIPHS                                                                 \
        AMEBA_PTIM_PERIPHS                                                                 \
        AMEBA_DMAC_PERIPHS                                                                 \
        AMEBA_SDH_PERIPHS                                                                  \
        AMEBA_SDD_PERIPHS                                                                  \
        AMEBA_SPI_PERIPHS                                                                  \
        AMEBA_USB_PERIPHS                                                                  \
        AMEBA_FLASH_PERIPHS                                                                \
        AMEBA_SPORT_PERIPHS                                                                \
        AMEBA_AC_PERIPHS                                                                   \
        AMEBA_I2C_PERIPHS                                                                  \
        AMEBA_TRNG_PERIPHS                                                                 \
        AMEBA_LCDC_PERIPHS                                                                 \
        AMEBA_A2C_PERIPHS                                                                  \
        AMEBA_GMAC_PERIPHS                                                                 \
        AMEBA_PPE_PERIPHS                                                                  \
        AMEBA_MJPEG_PERIPHS                                                                \
        AMEBA_BTON_PERIPHS

Aggregated core peripheral clock mappings.

This macro expands to mappings of all core peripherals used by the clock control implementation.

AMEBA_DMAC_CLK

#define AMEBA_DMAC_CLK   23

DMAC clock in SoC domain.

AMEBA_DMAC_PERIPHS

#define AMEBA_DMAC_PERIPHS   AMEBA_SINGLE_PERIPH(DMAC) /* AMEBA_DMAC_CLK */

DMAC clock peripheral mapping.

AMEBA_DTIM_CLK

#define AMEBA_DTIM_CLK   14

DTIM clock in SYSON domain.

AMEBA_FLASH_CLK

#define AMEBA_FLASH_CLK   29

Flash clock in SoC domain.

AMEBA_FLASH_PERIPHS

#define AMEBA_FLASH_PERIPHS   AMEBA_SINGLE_PERIPH(FLASH) /* AMEBA_FLASH_CLK */

Flash clock peripheral mapping.

AMEBA_GMAC_CLK

#define AMEBA_GMAC_CLK   40

GMAC clock in SoC domain.

AMEBA_GMAC_PERIPHS

#define AMEBA_GMAC_PERIPHS   AMEBA_SINGLE_PERIPH(GMAC) /* AMEBA_GMAC_CLK */

GMAC clock peripheral mapping.

AMEBA_GPIO_CLK

#define AMEBA_GPIO_CLK   16

GPIO clock in SYSON domain.

AMEBA_GPIO_PERIPHS

#define AMEBA_GPIO_PERIPHS   AMEBA_SINGLE_PERIPH(GPIO) /* AMEBA_GPIO_CLK */

GPIO clock peripheral mapping.

AMEBA_I2C0_CLK

#define AMEBA_I2C0_CLK   34

I2C0 clock in SoC domain.

AMEBA_I2C1_CLK

#define AMEBA_I2C1_CLK   35

I2C1 clock in SoC domain.

AMEBA_I2C_PERIPHS

#define AMEBA_I2C_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(I2C, 0) /* AMEBA_I2C0_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(I2C, 1) /* AMEBA_I2C1_CLK */

I2C clock peripheral mappings.

AMEBA_IRDA_CLK

#define AMEBA_IRDA_CLK   33

IRDA clock in SoC domain.

AMEBA_IRDA_PERIPHS

#define AMEBA_IRDA_PERIPHS   AMEBA_SINGLE_PERIPH(IRDA) /* AMEBA_IRDA_CLK */

IRDA clock peripheral mapping.

AMEBA_LCDC_CLK

#define AMEBA_LCDC_CLK   37

LCDC clock in SoC domain.

AMEBA_LCDC_PERIPHS

#define AMEBA_LCDC_PERIPHS   AMEBA_SINGLE_PERIPH(LCDC) /* AMEBA_LCDC_CLK */

LCDC clock peripheral mapping.

AMEBA_LEDC_CLK

#define AMEBA_LEDC_CLK   3

LEDC clock in AON domain.

AMEBA_LEDC_PERIPHS

#define AMEBA_LEDC_PERIPHS   AMEBA_SINGLE_PERIPH(LEDC) /* AMEBA_LEDC_CLK */

LEDC clock peripheral mapping.

AMEBA_LOGUART_CLK

#define AMEBA_LOGUART_CLK   13

LOGUART clock in SYSON domain.

AMEBA_LOGUART_PERIPHS

#define AMEBA_LOGUART_PERIPHS   AMEBA_SINGLE_PERIPH(LOGUART) /* AMEBA_LOGUART_CLK */

LOGUART clock peripheral mapping.

AMEBA_LTIM0_CLK

#define AMEBA_LTIM0_CLK   17

LTIM0 clock in SYSON domain.

AMEBA_LTIM1_CLK

#define AMEBA_LTIM1_CLK   18

LTIM1 clock in SYSON domain.

AMEBA_LTIM2_CLK

#define AMEBA_LTIM2_CLK   19

LTIM2 clock in SYSON domain.

AMEBA_LTIM3_CLK

#define AMEBA_LTIM3_CLK   20

LTIM3 clock in SYSON domain.

AMEBA_LTIM_PERIPHS

#define AMEBA_LTIM_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(LTIM, 0) /* AMEBA_LTIM0_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 1) /* AMEBA_LTIM1_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 2) /* AMEBA_LTIM2_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(LTIM, 3) /* AMEBA_LTIM3_CLK */

LTIM clock peripheral mappings.

AMEBA_MJPEG_CLK

#define AMEBA_MJPEG_CLK   42

MJPEG clock in SoC domain.

AMEBA_MJPEG_PERIPHS

#define AMEBA_MJPEG_PERIPHS   AMEBA_SINGLE_PERIPH(MJPEG) /* AMEBA_MJPEG_CLK */

MJPEG clock peripheral mapping.

AMEBA_NUMERICAL_PERIPH

#define AMEBA_NUMERICAL_PERIPH	(		name,
			n )

Value:

        [AMEBA_##name##n##_CLK] = {                                                        \
                .parent = AMEBA_RCC_NO_PARENT,                                             \
                .cke = APBPeriph_##name##n##_CLOCK,                                        \
                .fen = APBPeriph_##name##n,                                                \
        },

Define a clock entry for a peripheral with numerical suffix.

Used for peripherals with an index, for example SPI0, SPI1, UART0.

Parameters

name	Peripheral base name
n	Peripheral index

AMEBA_PKE_CLK

#define AMEBA_PKE_CLK   44

PKE clock (misc domain).

AMEBA_PPE_CLK

#define AMEBA_PPE_CLK   41

PPE clock in SoC domain.

AMEBA_PPE_PERIPHS

#define AMEBA_PPE_PERIPHS   AMEBA_SINGLE_PERIPH(PPE) /* AMEBA_PPE_CLK */

PPE clock peripheral mapping.

AMEBA_PSRAM_CLK

#define AMEBA_PSRAM_CLK   30

PSRAM clock in SoC domain.

AMEBA_PSRAM_PERIPHS

#define AMEBA_PSRAM_PERIPHS   AMEBA_SINGLE_PERIPH(PSRAM) /* AMEBA_PSRAM_CLK */

PSRAM clock peripheral mapping.

AMEBA_PTIM0_CLK

#define AMEBA_PTIM0_CLK   21

PTIM0 clock in SYSON domain.

AMEBA_PTIM1_CLK

#define AMEBA_PTIM1_CLK   22

PTIM1 clock in SYSON domain.

AMEBA_PTIM_PERIPHS

#define AMEBA_PTIM_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(PTIM, 0) /* AMEBA_PTIM0_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(PTIM, 1) /* AMEBA_PTIM1_CLK */

PTIM clock peripheral mappings.

AMEBA_PWM0_CLK

#define AMEBA_PWM0_CLK   4

PWM0 clock in SYSON domain.

AMEBA_PWM1_CLK

#define AMEBA_PWM1_CLK   5

PWM1 clock in SYSON domain.

AMEBA_PWM2_CLK

#define AMEBA_PWM2_CLK   6

PWM2 clock in SYSON domain.

AMEBA_PWM3_CLK

#define AMEBA_PWM3_CLK   7

PWM3 clock in SYSON domain.

AMEBA_PWM4_CLK

#define AMEBA_PWM4_CLK   8

PWM4 clock in SYSON domain.

AMEBA_PWM_PERIPHS

#define AMEBA_PWM_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(PWM, 0) /* AMEBA_PWM0_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(PWM, 1) /* AMEBA_PWM1_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(PWM, 2) /* AMEBA_PWM2_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(PWM, 3) /* AMEBA_PWM3_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(PWM, 4) /* AMEBA_PWM4_CLK */

PWM clock peripheral mappings.

AMEBA_RTC_CLK

#define AMEBA_RTC_CLK   2

RTC clock in AON domain.

AMEBA_RTC_PERIPHS

#define AMEBA_RTC_PERIPHS   AMEBA_SINGLE_PERIPH_NO_FEN(RTC) /* AMEBA_RTC_CLK */

RTC clock peripheral mapping (no FEN bit).

AMEBA_SDD_CLK

#define AMEBA_SDD_CLK   25

SDD clock in SoC domain.

AMEBA_SDD_PERIPHS

#define AMEBA_SDD_PERIPHS   AMEBA_SINGLE_PERIPH(SDD) /* AMEBA_SDD_CLK */

SDD clock peripheral mapping.

AMEBA_SDH_CLK

#define AMEBA_SDH_CLK   24

SDH clock in SoC domain.

AMEBA_SDH_PERIPHS

#define AMEBA_SDH_PERIPHS   AMEBA_SINGLE_PERIPH(SDH) /* AMEBA_SDH_CLK */

SDH clock peripheral mapping.

AMEBA_SINGLE_PERIPH

#define AMEBA_SINGLE_PERIPH

(

name

)

Value:

        [AMEBA_##name##_CLK] = {                                                           \
                .parent = AMEBA_RCC_NO_PARENT,                                             \
                .cke = APBPeriph_##name##_CLOCK,                                           \
                .fen = APBPeriph_##name,                                                   \
        },

Define a clock entry for a single-instance peripheral.

Used for peripherals that have only one instance, for example DMAC, SDH, SDD, USB, TRNG, etc.

Parameters

name	Peripheral name

AMEBA_SINGLE_PERIPH_NO_FEN

#define AMEBA_SINGLE_PERIPH_NO_FEN

(

name

)

Value:

        [AMEBA_##name##_CLK] = {                                                           \
                .parent = AMEBA_RCC_NO_PARENT,                                             \
                .cke = APBPeriph_##name##_CLOCK,                                           \
                .fen = APBPeriph_NULL,                                                     \
        },

Define a clock entry for a single-instance peripheral without FEN bit.

Used when a peripheral clock has no separate enable bit.

Parameters

name	Peripheral name

AMEBA_SPI0_CLK

#define AMEBA_SPI0_CLK   26

SPI0 clock in SoC domain.

AMEBA_SPI1_CLK

#define AMEBA_SPI1_CLK   27

SPI1 clock in SoC domain.

AMEBA_SPI_PERIPHS

#define AMEBA_SPI_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(SPI, 0) /* AMEBA_SPI0_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(SPI, 1) /* AMEBA_SPI1_CLK */

SPI clock peripheral mappings.

AMEBA_SPORT_CLK

#define AMEBA_SPORT_CLK   31

SPORT clock in SoC domain.

AMEBA_SPORT_PERIPHS

#define AMEBA_SPORT_PERIPHS   AMEBA_SINGLE_PERIPH(SPORT) /* AMEBA_SPORT_CLK */

SPORT clock peripheral mapping.

AMEBA_TRNG_CLK

#define AMEBA_TRNG_CLK   36

TRNG clock in SoC domain.

AMEBA_TRNG_PERIPHS

#define AMEBA_TRNG_PERIPHS   AMEBA_SINGLE_PERIPH(TRNG) /* AMEBA_TRNG_CLK */

TRNG clock peripheral mapping.

AMEBA_UART0_CLK

#define AMEBA_UART0_CLK   9

UART0 clock in SYSON domain.

AMEBA_UART1_CLK

#define AMEBA_UART1_CLK   10

UART1 clock in SYSON domain.

AMEBA_UART2_CLK

#define AMEBA_UART2_CLK   11

UART2 clock in SYSON domain.

AMEBA_UART3_CLK

#define AMEBA_UART3_CLK   12

UART3 clock in SYSON domain.

AMEBA_UART_PERIPHS

#define AMEBA_UART_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(UART, 0) /* AMEBA_UART0_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(UART, 1) /* AMEBA_UART1_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(UART, 2) /* AMEBA_UART2_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(UART, 3) /* AMEBA_UART3_CLK */

UART clock peripheral mappings.

AMEBA_USB_CLK

#define AMEBA_USB_CLK   28

USB clock in SoC domain.

AMEBA_USB_PERIPHS

#define AMEBA_USB_PERIPHS   AMEBA_SINGLE_PERIPH(USB) /* AMEBA_USB_CLK */

USB clock peripheral mapping.