Zephyr API Documentation 3.7.99
A Scalable Open Source RTOS
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Driver for ARM Generic Interrupt Controller. More...
Go to the source code of this file.
Functions | |
void | arm_gic_irq_enable (unsigned int irq) |
Enable interrupt. | |
void | arm_gic_irq_disable (unsigned int irq) |
Disable interrupt. | |
bool | arm_gic_irq_is_enabled (unsigned int irq) |
Check if an interrupt is enabled. | |
bool | arm_gic_irq_is_pending (unsigned int irq) |
Check if an interrupt is pending. | |
void | arm_gic_irq_set_pending (unsigned int irq) |
Set interrupt as pending. | |
void | arm_gic_irq_clear_pending (unsigned int irq) |
Clear the pending irq. | |
void | arm_gic_irq_set_priority (unsigned int irq, unsigned int prio, unsigned int flags) |
Set interrupt priority. | |
unsigned int | arm_gic_get_active (void) |
Get active interrupt ID. | |
void | arm_gic_eoi (unsigned int irq) |
Signal end-of-interrupt. | |
void | arm_gic_secondary_init (void) |
Initialize GIC of secondary cores. | |
void | gic_raise_sgi (unsigned int sgi_id, uint64_t target_aff, uint16_t target_list) |
raise SGI to target cores | |
Driver for ARM Generic Interrupt Controller.
The Generic Interrupt Controller (GIC) is the default interrupt controller for the ARM A and R profile cores. This driver is used by the ARM arch implementation to handle interrupts.
#define GIC_CPU_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1) |
#define GIC_DIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0) |
#define GIC_IDLE_PRIO 0xff |
#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0 |
#define GIC_INTID_SPURIOUS 1023 |
#define GIC_IS_SGI | ( | intid | ) |
#define GIC_IS_SPI | ( | intid | ) |
#define GIC_NUM_CFG_PER_REG 16 |
#define GIC_NUM_CPU_IF CONFIG_MP_MAX_NUM_CPUS |
#define GIC_NUM_INTR_PER_REG 32 |
#define GIC_NUM_PRI_PER_REG 4 |
#define GIC_PPI_INT_BASE 16 |
#define GIC_PRI_MASK 0xff |
#define GIC_SGI_INT_BASE 0 |
#define GIC_SPI_INT_BASE 32 |
#define GIC_SPI_MAX_INTID 1019 |
#define GICC_BPR (GIC_CPU_BASE + 0x8) |
#define GICC_CTLR (GIC_CPU_BASE + 0x0) |
#define GICC_CTLR_ENABLE_MASK (GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1) |
#define GICC_CTLR_ENABLEGRP0 BIT(0) |
#define GICC_CTLR_ENABLEGRP1 BIT(1) |
#define GICC_EOIR (GIC_CPU_BASE + 0x10) |
#define GICC_IAR (GIC_CPU_BASE + 0xc) |
#define GICC_PMR (GIC_CPU_BASE + 0x4) |
#define GICD_CTLR (GIC_DIST_BASE + 0x0) |
#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180) |
#define GICD_ICFGR_MASK BIT_MASK(2) |
#define GICD_ICFGR_TYPE BIT(1) |
#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00) |
#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280) |
#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80) |
#define GICD_IIDR (GIC_DIST_BASE + 0x8) |
#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400) |
#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300) |
#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100) |
#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200) |
#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800) |
#define GICD_SGIR (GIC_DIST_BASE + 0xf00) |
#define GICD_SGIR_CPULIST | ( | x | ) |
#define GICD_SGIR_CPULIST_CPU | ( | n | ) |
#define GICD_SGIR_CPULIST_MASK 0xff |
#define GICD_SGIR_NSATT BIT(15) |
#define GICD_SGIR_SGIINTID | ( | x | ) |
#define GICD_SGIR_TGTFILT | ( | x | ) |
#define GICD_SGIR_TGTFILT_ALLBUTREQ GICD_SGIR_TGTFILT(0b01) |
#define GICD_SGIR_TGTFILT_CPULIST GICD_SGIR_TGTFILT(0b00) |
#define GICD_SGIR_TGTFILT_REQONLY GICD_SGIR_TGTFILT(0b10) |
#define GICD_TYPER (GIC_DIST_BASE + 0x4) |
#define GICD_TYPER_IDBITS | ( | typer | ) |
#define GICD_TYPER_ITLINESNUM_MASK 0x1f |
void arm_gic_eoi | ( | unsigned int | irq | ) |
Signal end-of-interrupt.
irq | interrupt ID |
unsigned int arm_gic_get_active | ( | void | ) |
Get active interrupt ID.
void arm_gic_irq_clear_pending | ( | unsigned int | irq | ) |
Clear the pending irq.
irq | interrupt ID |
void arm_gic_irq_disable | ( | unsigned int | irq | ) |
Disable interrupt.
irq | interrupt ID |
void arm_gic_irq_enable | ( | unsigned int | irq | ) |
Enable interrupt.
irq | interrupt ID |
Check if an interrupt is enabled.
irq | interrupt ID |
Check if an interrupt is pending.
irq | interrupt ID |
void arm_gic_irq_set_pending | ( | unsigned int | irq | ) |
Set interrupt as pending.
irq | interrupt ID |
Set interrupt priority.
irq | interrupt ID |
prio | interrupt priority |
flags | interrupt flags |
void arm_gic_secondary_init | ( | void | ) |
Initialize GIC of secondary cores.