mchp_clock_sam_d5x_e5x.h

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/*
 * Copyright (c) 2025 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_SAM_D5X_E5X_H_
#define INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_SAM_D5X_E5X_H_
 
#include <zephyr/dt-bindings/clock/mchp_sam_d5x_e5x_clock.h>


struct clock_mchp_subsys_xosc_config {
        bool on_demand_en;

        bool run_in_standby_en;
};

enum clock_mchp_gclkgen {
        CLOCK_MCHP_GCLKGEN_GEN0,  
        CLOCK_MCHP_GCLKGEN_GEN1,  
        CLOCK_MCHP_GCLKGEN_GEN2,  
        CLOCK_MCHP_GCLKGEN_GEN3,  
        CLOCK_MCHP_GCLKGEN_GEN4,  
        CLOCK_MCHP_GCLKGEN_GEN5,  
        CLOCK_MCHP_GCLKGEN_GEN6,  
        CLOCK_MCHP_GCLKGEN_GEN7,  
        CLOCK_MCHP_GCLKGEN_GEN8,  
        CLOCK_MCHP_GCLKGEN_GEN9,  
        CLOCK_MCHP_GCLKGEN_GEN10, 
        CLOCK_MCHP_GCLKGEN_GEN11  
};

struct clock_mchp_subsys_dfll_config {
        bool on_demand_en;

        bool run_in_standby_en;

        bool closed_loop_en;

        enum clock_mchp_gclkgen src;

        uint32_t multiply_factor;
};

enum clock_mchp_fdpll_src_clock {
        CLOCK_MCHP_FDPLL_SRC_GCLK0,   
        CLOCK_MCHP_FDPLL_SRC_GCLK1,   
        CLOCK_MCHP_FDPLL_SRC_GCLK2,   
        CLOCK_MCHP_FDPLL_SRC_GCLK3,   
        CLOCK_MCHP_FDPLL_SRC_GCLK4,   
        CLOCK_MCHP_FDPLL_SRC_GCLK5,   
        CLOCK_MCHP_FDPLL_SRC_GCLK6,   
        CLOCK_MCHP_FDPLL_SRC_GCLK7,   
        CLOCK_MCHP_FDPLL_SRC_GCLK8,   
        CLOCK_MCHP_FDPLL_SRC_GCLK9,   
        CLOCK_MCHP_FDPLL_SRC_GCLK10,  
        CLOCK_MCHP_FDPLL_SRC_GCLK11,  
        CLOCK_MCHP_FDPLL_SRC_XOSC32K, 
        CLOCK_MCHP_FDPLL_SRC_XOSC0,   
        CLOCK_MCHP_FDPLL_SRC_XOSC1,   
 
        CLOCK_MCHP_FDPLL_SRC_MAX = CLOCK_MCHP_FDPLL_SRC_XOSC1 
};

struct clock_mchp_subsys_fdpll_config {
        bool on_demand_en;

        bool run_in_standby_en;

        enum clock_mchp_fdpll_src_clock src;

        uint32_t xosc_clock_divider;

        uint32_t divider_ratio_int;

        uint32_t divider_ratio_frac;
};

enum clock_mchp_rtc_src_clock {
        CLOCK_MCHP_RTC_SRC_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K,
        CLOCK_MCHP_RTC_SRC_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K,
        CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K,
        CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K
};

struct clock_mchp_subsys_rtc_config {
        enum clock_mchp_rtc_src_clock src;
};

struct clock_mchp_subsys_xosc32k_config {
        bool on_demand_en;

        bool run_in_standby_en;
};

enum clock_mchp_gclk_src_clock {
        CLOCK_MCHP_GCLK_SRC_XOSC0,     
        CLOCK_MCHP_GCLK_SRC_XOSC1,     
        CLOCK_MCHP_GCLK_SRC_GCLKPIN,   
        CLOCK_MCHP_GCLK_SRC_GCLKGEN1,  
        CLOCK_MCHP_GCLK_SRC_OSCULP32K, 
        CLOCK_MCHP_GCLK_SRC_XOSC32K,   
        CLOCK_MCHP_GCLK_SRC_DFLL,      
        CLOCK_MCHP_GCLK_SRC_FDPLL0,    
        CLOCK_MCHP_GCLK_SRC_FDPLL1,    
 
        CLOCK_MCHP_GCLK_SRC_MAX = CLOCK_MCHP_GCLK_SRC_FDPLL1 
};

struct clock_mchp_subsys_gclkgen_config {
        bool run_in_standby_en;

        enum clock_mchp_gclk_src_clock src;

        uint16_t div_factor;
};

struct clock_mchp_subsys_gclkperiph_config {
        enum clock_mchp_gclkgen src;
};

enum clock_mchp_mclk_cpu_div {
        CLOCK_MCHP_MCLK_CPU_DIV_1 = 1,    
        CLOCK_MCHP_MCLK_CPU_DIV_2 = 2,    
        CLOCK_MCHP_MCLK_CPU_DIV_4 = 4,    
        CLOCK_MCHP_MCLK_CPU_DIV_8 = 8,    
        CLOCK_MCHP_MCLK_CPU_DIV_16 = 16,  
        CLOCK_MCHP_MCLK_CPU_DIV_32 = 32,  
        CLOCK_MCHP_MCLK_CPU_DIV_64 = 64,  
        CLOCK_MCHP_MCLK_CPU_DIV_128 = 128 
};

struct clock_mchp_subsys_mclkcpu_config {
        enum clock_mchp_mclk_cpu_div division_factor;
};

typedef uint32_t *clock_mchp_rate_t;

 
#endif /* INCLUDE_ZEPHYR_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_SAM_D5X_E5X_H_ */