Microchip PIC32CZ CA

Files
file	mchp_clock_pic32cz_ca.h
	Clock control header file for the Microchip PIC32CZ CA family.

Data Structures
struct	clock_mchp_subsys_xosc_config
	External oscillator (XOSC) configuration. More...
struct	clock_mchp_subsys_dfll48m_config
	DFLL 48MHz configuration structure. More...
struct	clock_mchp_subsys_dpll_config
	DPLL configuration structure. More...
struct	clock_mchp_subsys_dpll_out_config
	DPLL Output configuration structure. More...
struct	clock_mchp_subsys_rtc_config
	RTC clock configuration. More...
struct	clock_mchp_subsys_xosc32k_config
	32 kHz external oscillator (XOSC32K) configuration. More...
struct	clock_mchp_subsys_gclkgen_config
	GCLK generator configuration. More...
struct	clock_mchp_subsys_gclkperiph_config
	Peripheral GCLK channel configuration. More...
struct	clock_mchp_subsys_mclkcpu_config
	MCLK configuration structure. More...

Typedefs
typedef uint32_t *	clock_mchp_rate_t
	clock rate datatype

Enumerations
enum	clock_mchp_gclkgen {   CLOCK_MCHP_GCLKGEN_GEN0 , CLOCK_MCHP_GCLKGEN_GEN1 , CLOCK_MCHP_GCLKGEN_GEN2 , CLOCK_MCHP_GCLKGEN_GEN3 ,   CLOCK_MCHP_GCLKGEN_GEN4 , CLOCK_MCHP_GCLKGEN_GEN5 , CLOCK_MCHP_GCLKGEN_GEN6 , CLOCK_MCHP_GCLKGEN_GEN7 ,   CLOCK_MCHP_GCLKGEN_GEN8 , CLOCK_MCHP_GCLKGEN_GEN9 , CLOCK_MCHP_GCLKGEN_GEN10 , CLOCK_MCHP_GCLKGEN_GEN11 ,   CLOCK_MCHP_GCLKGEN_GEN12 , CLOCK_MCHP_GCLKGEN_GEN13 , CLOCK_MCHP_GCLKGEN_GEN14 , CLOCK_MCHP_GCLKGEN_GEN15 }
	Gclk generator numbers. More...
enum	clock_mchp_dpll_src_clock {   CLOCK_MCHP_DPLL_SRC_GCLK0 , CLOCK_MCHP_DPLL_SRC_GCLK1 , CLOCK_MCHP_DPLL_SRC_GCLK2 , CLOCK_MCHP_DPLL_SRC_GCLK3 ,   CLOCK_MCHP_DPLL_SRC_GCLK4 , CLOCK_MCHP_DPLL_SRC_GCLK5 , CLOCK_MCHP_DPLL_SRC_GCLK6 , CLOCK_MCHP_DPLL_SRC_GCLK7 ,   CLOCK_MCHP_DPLL_SRC_GCLK8 , CLOCK_MCHP_DPLL_SRC_GCLK9 , CLOCK_MCHP_DPLL_SRC_GCLK10 , CLOCK_MCHP_DPLL_SRC_GCLK11 ,   CLOCK_MCHP_DPLL_SRC_GCLK12 , CLOCK_MCHP_DPLL_SRC_GCLK13 , CLOCK_MCHP_DPLL_SRC_GCLK14 , CLOCK_MCHP_DPLL_SRC_GCLK15 ,   CLOCK_MCHP_DPLL_SRC_XOSC , CLOCK_MCHP_DPLL_SRC_DFLL48M , CLOCK_MCHP_DPLL_SRC_MAX }
	DPLL source clocks. More...
enum	clock_mchp_rtc_src_clock { CLOCK_MCHP_RTC_SRC_ULP1K = OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP1K_Val , CLOCK_MCHP_RTC_SRC_ULP32K = OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP32K_Val , CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC1K_Val , CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC32K_Val }
	RTC source clocks. More...
enum	clock_mchp_gclk_src_clock {   CLOCK_MCHP_GCLK_SRC_XOSC , CLOCK_MCHP_GCLK_SRC_GCLKPIN , CLOCK_MCHP_GCLK_SRC_GCLKGEN1 , CLOCK_MCHP_GCLK_SRC_OSCULP32K ,   CLOCK_MCHP_GCLK_SRC_XOSC32K , CLOCK_MCHP_GCLK_SRC_DFLL48M , CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT0 , CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT1 ,   CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT2 , CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT3 , CLOCK_MCHP_GCLK_SRC_DPLL1_FRC_CLKOUT0 , CLOCK_MCHP_GCLK_SRC_DPLL1_FRC_CLKOUT1 ,   CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT2 , CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT3 , CLOCK_MCHP_GCLK_SRC_MAX }
	Gclk Generator source clocks. More...
enum	clock_mchp_mclk_cpu_div {   CLOCK_MCHP_MCLK_CPU_DIV_1 = 1 , CLOCK_MCHP_MCLK_CPU_DIV_2 = 2 , CLOCK_MCHP_MCLK_CPU_DIV_4 = 4 , CLOCK_MCHP_MCLK_CPU_DIV_8 = 8 ,   CLOCK_MCHP_MCLK_CPU_DIV_16 = 16 , CLOCK_MCHP_MCLK_CPU_DIV_32 = 32 , CLOCK_MCHP_MCLK_CPU_DIV_64 = 64 , CLOCK_MCHP_MCLK_CPU_DIV_128 = 128 }
	division ratio of mclk prescaler for CPU More...

Detailed Description

Typedef Documentation

clock_mchp_rate_t

typedef uint32_t* clock_mchp_rate_t

#include <zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h>

clock rate datatype

Used for setting a clock rate

Enumeration Type Documentation

clock_mchp_dpll_src_clock

enum clock_mchp_dpll_src_clock

#include <zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h>

DPLL source clocks.

Enumerator
CLOCK_MCHP_DPLL_SRC_GCLK0	Gclk Generator 0.
CLOCK_MCHP_DPLL_SRC_GCLK1	Gclk Generator 1.
CLOCK_MCHP_DPLL_SRC_GCLK2	Gclk Generator 2.
CLOCK_MCHP_DPLL_SRC_GCLK3	Gclk Generator 3.
CLOCK_MCHP_DPLL_SRC_GCLK4	Gclk Generator 4.
CLOCK_MCHP_DPLL_SRC_GCLK5	Gclk Generator 5.
CLOCK_MCHP_DPLL_SRC_GCLK6	Gclk Generator 6.
CLOCK_MCHP_DPLL_SRC_GCLK7	Gclk Generator 7.
CLOCK_MCHP_DPLL_SRC_GCLK8	Gclk Generator 8.
CLOCK_MCHP_DPLL_SRC_GCLK9	Gclk Generator 9.
CLOCK_MCHP_DPLL_SRC_GCLK10	Gclk Generator 10.
CLOCK_MCHP_DPLL_SRC_GCLK11	Gclk Generator 11.
CLOCK_MCHP_DPLL_SRC_GCLK12	Gclk Generator 12.
CLOCK_MCHP_DPLL_SRC_GCLK13	Gclk Generator 13.
CLOCK_MCHP_DPLL_SRC_GCLK14	Gclk Generator 14.
CLOCK_MCHP_DPLL_SRC_GCLK15	Gclk Generator 15.
CLOCK_MCHP_DPLL_SRC_XOSC	External crystal oscillator (XOSC).
CLOCK_MCHP_DPLL_SRC_DFLL48M	Internal 48 MHz DFLL clock.
CLOCK_MCHP_DPLL_SRC_MAX	Maximum valid DPLL source clock.

clock_mchp_gclk_src_clock

enum clock_mchp_gclk_src_clock

#include <zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h>

Gclk Generator source clocks.

Enumerator
CLOCK_MCHP_GCLK_SRC_XOSC	External crystal oscillator (XOSC).
CLOCK_MCHP_GCLK_SRC_GCLKPIN	External clock input from Gclk I/O pin.
CLOCK_MCHP_GCLK_SRC_GCLKGEN1	Output of Generic Clock Generator 1.
CLOCK_MCHP_GCLK_SRC_OSCULP32K	Internal ultra-low-power 32 kHz oscillator.
CLOCK_MCHP_GCLK_SRC_XOSC32K	External 32.768 kHz crystal oscillator.
CLOCK_MCHP_GCLK_SRC_DFLL48M	Internal 48 MHz DFLL clock.
CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT0	DPLL0 output clock 0.
CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT1	DPLL0 output clock 1.
CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT2	DPLL0 output clock 2.
CLOCK_MCHP_GCLK_SRC_DPLL0_CLKOUT3	DPLL0 output clock 3.
CLOCK_MCHP_GCLK_SRC_DPLL1_FRC_CLKOUT0	DPLL1 clock output 0.
CLOCK_MCHP_GCLK_SRC_DPLL1_FRC_CLKOUT1	DPLL1 clock output 1.
CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT2	DPLL1 output clock 2.
CLOCK_MCHP_GCLK_SRC_DPLL1_CLKOUT3	DPLL1 output clock 3.
CLOCK_MCHP_GCLK_SRC_MAX	Maximum valid Gclk source.

clock_mchp_gclkgen

enum clock_mchp_gclkgen

#include <zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h>

Gclk generator numbers.

Enumerator
CLOCK_MCHP_GCLKGEN_GEN0	Gclk Generator 0.
CLOCK_MCHP_GCLKGEN_GEN1	Gclk Generator 1.
CLOCK_MCHP_GCLKGEN_GEN2	Gclk Generator 2.
CLOCK_MCHP_GCLKGEN_GEN3	Gclk Generator 3.
CLOCK_MCHP_GCLKGEN_GEN4	Gclk Generator 4.
CLOCK_MCHP_GCLKGEN_GEN5	Gclk Generator 5.
CLOCK_MCHP_GCLKGEN_GEN6	Gclk Generator 6.
CLOCK_MCHP_GCLKGEN_GEN7	Gclk Generator 7.
CLOCK_MCHP_GCLKGEN_GEN8	Gclk Generator 8.
CLOCK_MCHP_GCLKGEN_GEN9	Gclk Generator 9.
CLOCK_MCHP_GCLKGEN_GEN10	Gclk Generator 10.
CLOCK_MCHP_GCLKGEN_GEN11	Gclk Generator 11.
CLOCK_MCHP_GCLKGEN_GEN12	Gclk Generator 12.
CLOCK_MCHP_GCLKGEN_GEN13	Gclk Generator 13.
CLOCK_MCHP_GCLKGEN_GEN14	Gclk Generator 14.
CLOCK_MCHP_GCLKGEN_GEN15	Gclk Generator 15.

clock_mchp_mclk_cpu_div

enum clock_mchp_mclk_cpu_div

#include <zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h>

division ratio of mclk prescaler for CPU

Enumerator
CLOCK_MCHP_MCLK_CPU_DIV_1	Divide by 1 (no division).
CLOCK_MCHP_MCLK_CPU_DIV_2	Divide by 2.
CLOCK_MCHP_MCLK_CPU_DIV_4	Divide by 4.
CLOCK_MCHP_MCLK_CPU_DIV_8	Divide by 8.
CLOCK_MCHP_MCLK_CPU_DIV_16	Divide by 16.
CLOCK_MCHP_MCLK_CPU_DIV_32	Divide by 32.
CLOCK_MCHP_MCLK_CPU_DIV_64	Divide by 64.
CLOCK_MCHP_MCLK_CPU_DIV_128	Divide by 128.

clock_mchp_rtc_src_clock

enum clock_mchp_rtc_src_clock

#include <zephyr/drivers/clock_control/mchp_clock_pic32cz_ca.h>

RTC source clocks.

Enumerator
CLOCK_MCHP_RTC_SRC_ULP1K	Internal ultra-low-power 1 kHz oscillator.
CLOCK_MCHP_RTC_SRC_ULP32K	Internal ultra-low-power 32 kHz oscillator.
CLOCK_MCHP_RTC_SRC_XOSC1K	External crystal oscillator divided to 1 kHz.
CLOCK_MCHP_RTC_SRC_XOSC32K	External 32.768 kHz crystal oscillator.